JPS618953A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS618953A
JPS618953A JP13045284A JP13045284A JPS618953A JP S618953 A JPS618953 A JP S618953A JP 13045284 A JP13045284 A JP 13045284A JP 13045284 A JP13045284 A JP 13045284A JP S618953 A JPS618953 A JP S618953A
Authority
JP
Japan
Prior art keywords
insulating film
wafer
steps
difference
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13045284A
Other languages
Japanese (ja)
Inventor
Yasuo Ooyama
大山 泰男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13045284A priority Critical patent/JPS618953A/en
Publication of JPS618953A publication Critical patent/JPS618953A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Abstract

PURPOSE:To decrease the difference in steps only by the simple change in processes and by the change in conditions without using silica or a new material such as high viscosity macromelecular material, by using anisotropic etching, and making a thin film to remain around the difference in steps. CONSTITUTION:An insulating film 5 is laminated so as to cover a wiring 1, which is extended on an insulating film of a semiconductor wafer. The thickness of the insulating film 5 in the direction perpendicular to the wafer around the difference in steps is shown by a numeral 6. The thickness of the film at a flat part in the direction perpendicular to the wafer is shown by a numeral 7. The width 7 is thinner than the thickness 6. Anisotropic etching having the etching characteristic perpendicular to the wafer is performed for the wafer by the etching amount of the thickness 6 or less, under the condition the etching rate of the insulating film is higher than a wiring material 1. Then, a part 8 of the insulating film 5 remains around the difference in steps. Thereafter, another insulating film 9 is formed, and a sputtered or evaporated metal 10 is formed.

Description

【発明の詳細な説明】 (1)発明の属する技術分野 本発明は半導体装置の製造方法に関し、配線などの急峻
な段差に対し、その後積層する膜のカバーレッジを改善
する半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that improves the coverage of a subsequently laminated film for steep steps such as wiring. .

(2)従来技術の説明 ウェハー表面の段差に対し、各種材料を積層していくと
、除々にカバーレッジが悪くなってくる。
(2) Description of the Prior Art As various materials are stacked on top of the steps on the wafer surface, the coverage gradually deteriorates.

特に蒸着、又はスパッタで成長させる金属に対してはそ
の傾向が顕著である。第1図はその例を示したものであ
る。配線1上に通常カバーレッジがもともと良いと言わ
れる、CvDで成長させた絶縁層2を設け、その上に上
部の配線に使用する蒸着などで成長させた金属3を形成
する。この場合部分4は非常に薄くなりこのため第2層
目の金属3で作成する配線の断線原因となる。
This tendency is particularly noticeable for metals grown by vapor deposition or sputtering. FIG. 1 shows an example of this. An insulating layer 2 grown by CVD, which is said to have good coverage, is provided on the wiring 1, and a metal 3 grown by vapor deposition or the like used for the upper wiring is formed thereon. In this case, the portion 4 becomes extremely thin, which may cause a break in the wiring formed using the second layer of metal 3.

これを改善する方法として、シリカ又は、高粘度高分子
材料を用いて1段差形成後塗布し、段差をなだらかにし
、カバーレッジの向上を計ろうとする方法がある。
As a method to improve this, there is a method in which silica or a high viscosity polymeric material is applied after forming one level difference to smoothen the level difference and improve coverage.

しかし、この方法では、新しい材料、新しい装置をそろ
える必要があり、又、新しい材料の半導体装置に与える
影舎も確認する必要があり、簡単な工程変更及び条件変
更では、実施できない欠点がおった。
However, with this method, it is necessary to prepare new materials and new equipment, and it is also necessary to check the effects on semiconductor devices made of new materials, which has the disadvantage that it cannot be implemented with simple process changes and condition changes. .

(3)発明の詳細な説明 本発明の目的は、特に新しい材料を使用することなしに
配線による急峻な段差をなだらかにし、上部に積層する
金属のカバーレッジを簡単な工程変更2条件変更のみで
行える様にした半導体装置の製造方法を提供することに
ある。
(3) Detailed Description of the Invention The purpose of the present invention is to smooth out steep steps caused by wiring without using new materials, and to change the metal coverage layered on top by simply changing the process and changing two conditions. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be performed.

(4)発明の構成 本発明は、急峻な段を持つ配線などの段差に対し、全面
に絶縁膜を成長させ、ウェハーに対し、垂直方向にエツ
チングができる異方性エッチを用いて、その急峻な段差
周囲にのみ絶縁膜を残し、段差をなだらかにすることに
より、さらに上部に積層する薄膜に対して、カバーレッ
ジを改善させ6゜   i この様な方法によって得られた半導体装置は、シリカ又
は、高分子材料を使用せず、従来がら使用してきたCv
D成長などで得られる絶縁膜をそのまま段差低減に用い
ることができ、簡単な工程′      変更2条件変
更により、積層する薄膜のカバーレッジを改善すること
ができる。
(4) Structure of the Invention The present invention grows an insulating film over the entire surface of a wiring that has a steep step, and uses anisotropic etching that can be etched perpendicularly to the wafer. By leaving the insulating film only around the steps and making the steps gentle, the coverage is improved for the thin film laminated on top. , Cv, which has been conventionally used without using polymeric materials.
The insulating film obtained by D-growth etc. can be used as it is to reduce the step difference, and the coverage of the thin films to be laminated can be improved by a simple process change and two condition changes.

(5)  発明の原理と作用の説明 急峻な段差に対し、それを覆う様に薄膜を成長させ、そ
の後ウェハー表面に対して垂直なエツチング特性を持つ
異方性エツチングでウェハー全面にエツチングを行うと
、段差部側面でのウェハー垂直方向の膜厚は、他の部分
に比較して厚いため、エツチング時間を調整することに
より段差部周囲にのみ薄膜を残すことができ、等測的に
急峻な段をなだらかにすることができる。
(5) Explanation of the principle and operation of the invention A thin film is grown to cover a steep step, and then the entire surface of the wafer is etched using anisotropic etching, which has etching characteristics perpendicular to the wafer surface. The thickness of the film in the vertical direction of the wafer on the side surface of the step is thicker than on other parts, so by adjusting the etching time, it is possible to leave a thin film only around the step. can be made gentler.

(6)発明の詳細な説明 次に本発明の実施例について、順番に段面図を参照し、
説明する。
(6) Detailed Description of the Invention Next, referring to the step drawings in order regarding the embodiments of the present invention,
explain.

まず第2図を参照すると、半導体ウェハー上の絶縁膜上
を延在する配M1を覆うように絶縁膜5を積層する。こ
こで絶縁膜50段差周囲のウェハーに垂直な方向の厚さ
を6で示し、平坦部でのウェハーに垂直な方向の厚さを
7で示している。ここで6より7の方が薄いため、この
ウェハーに対       やし、つ8・・−に垂直な
一2チ・グ特性を持つ異方       ″−性エッチ
ングを絶縁膜のエッチレートが1の配線材料より高い条
件で、エツチング量として、厚さ6以下行うと第3図と
なる。第3図において段差周囲には絶縁膜5の部分8が
残余する。次に第4図に示すように他の絶縁膜9を形成
し、そして第5図に示すようにスパッタ又は蒸着した金
属10を形成する。
First, referring to FIG. 2, the insulating film 5 is laminated to cover the wiring M1 extending over the insulating film on the semiconductor wafer. Here, the thickness in the direction perpendicular to the wafer around the insulating film 50 step difference is indicated by 6, and the thickness in the direction perpendicular to the wafer at the flat portion is indicated by 7. Here, since 7 is thinner than 6, anisotropic etching with a 12-chip characteristic perpendicular to 8...- is performed on this wafer for interconnects with an etch rate of 1 for the insulating film. If etching is performed to a thickness of 6 or less under conditions higher than the material, the result will be as shown in Fig. 3. In Fig. 3, a portion 8 of the insulating film 5 remains around the step. Then, as shown in FIG. 5, a sputtered or vapor deposited metal 10 is formed.

ここで第1図と第5図とを比較すると、部分8が段差低
減効果を持ち、第5図の構造の方が、カバーレッジを大
幅に改善できることがわかる。この時絶縁膜5による部
分8の材質が絶縁膜9と同じであれば、あたかも、絶縁
膜9のカバーレッジが、変化しただけに見え、材質的に
信頼性を確認する必要はな〈従来の製造プロセスに対し
、簡単に適用できる。
Comparing FIG. 1 with FIG. 5, it can be seen that the portion 8 has an effect of reducing the level difference, and the structure of FIG. 5 can significantly improve the coverage. At this time, if the material of the portion 8 formed by the insulating film 5 is the same as that of the insulating film 9, it will appear as if the coverage of the insulating film 9 has simply changed, and there is no need to confirm the reliability of the material. Easy to apply to manufacturing processes.

第6図は、本発明をさらに発展させたもので、第3図の
状態になった後、第2図と同様に全体に他の絶縁膜を成
長させ、その絶縁膜を段差周囲に残す様に、異方性エッ
チを行ったもので、11はその絶縁膜の残りである。こ
の様にすると、第3図に比較して、さらに大きな段差低
減効果が期待でき、同様にくり返すことによって、段だ
らし状態を必要に応じて変化させることができる。
Figure 6 shows a further development of the present invention, in which, after reaching the state shown in Figure 3, another insulating film is grown over the entire surface as in Figure 2, and that insulating film is left around the step. 11 is the remainder of the insulating film. By doing this, a greater level difference reduction effect can be expected compared to that shown in FIG. 3, and by repeating the same process, the level sloping state can be changed as necessary.

(7)発明の詳細な説明 本発明は以上説明した様に異方性エツチング用いて、段
差周囲にのみ薄膜を残すことによってシリカ又は、高粘
度高分子材料など新しい材料などを使用することなしに
、簡単な工程変更9条件変更のみで段差を低減させる効
果がある。
(7) Detailed description of the invention As explained above, the present invention uses anisotropic etching to leave a thin film only around the steps, thereby eliminating the need for new materials such as silica or high-viscosity polymer materials. It is effective to reduce the difference in level with only 9 simple process changes and condition changes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、段差低減の方法を使用していない場合の、積
層した薄膜の状態を示す断面図である。 第2図乃至第5図は、本発明の第1の実施例を示す断面
図であり、第3図は、第2図の表面の絶縁膜を異方性エ
ツチングを用いて、段差周囲にのみ残る様にエツチング
した断面図であり、第4図は第3図の表面に絶縁膜を積
層した断面図であり、第5図は第4図の表面にカバーレ
ッジが悪い金属を積層した段面図である。 第6図は本発明の第2の実施例を示すもので第3図の様
に段部が、作成された後さらに絶縁膜を成長させ、異方
性エッチで、段差周囲にのみ残る様にエツチングした断
面図である。 尚、図において、1・・・・・・急峻な段を持つ配線、
2°゛°°°・1を被うカバーレッジの良いCVD成長
などによる絶縁膜、3・・・・・・2の上部に積層した
カバーレッジが悪い蒸着膜などによる金属膜、4・・・
・・・3が段差の影曽により非常に薄くなっている部分
、5・・・・・・1を被うカバーレッジの良いCVD成
長による絶縁膜、6・・・・・・1の段差周囲でのウェ
ハーに垂直な方向の5の高さ、7・・・・・・平坦部で
の5の高さ、8・・・・・・異方性エッチに、よって1
の段差周囲にだけ残った絶縁膜5の部分、9・・・・・
・1と8を被うカバーレッジの良い(、VD成長による
絶縁膜、10・・・・・・9の上部に積層したカバーレ
ッジが悪い蒸着膜などによる金属膜、11・・・・パ第
3図の様に段部が形成された後、さらに他の絶MjR膜
を成長させ異方性エッチによって、1及び8の段差周囲
に残った他の絶縁膜の部分である。 千1図 第2図 千3図
FIG. 1 is a cross-sectional view showing the state of laminated thin films when no step reduction method is used. 2 to 5 are cross-sectional views showing the first embodiment of the present invention, and FIG. 3 shows an insulating film on the surface of FIG. 2 by anisotropic etching, only around the steps. Fig. 4 is a cross-sectional view of an insulating film laminated on the surface of Fig. 3, and Fig. 5 is a cross-sectional view of a stepped surface in which a metal with poor coverage is laminated on the surface of Fig. 4. It is a diagram. FIG. 6 shows a second embodiment of the present invention. After the stepped portion is created as shown in FIG. 3, an insulating film is further grown and anisotropically etched so that it remains only around the stepped portion. FIG. 3 is an etched cross-sectional view. In addition, in the figure, 1... Wiring with steep steps,
2°゛°°°・An insulating film grown by CVD or the like with good coverage covering 1, 3... A metal film such as a vapor deposited film with poor coverage laminated on top of 2, 4...
...3 is a part that is extremely thin due to the shadow of the step, 5...is an insulating film grown by CVD with good coverage covering 1, 6... is the area around the step 1 5 height in the direction perpendicular to the wafer at
The portion of the insulating film 5 remaining only around the step, 9...
・Good coverage covering 1 and 8 (insulating film by VD growth, 10...Metal film such as vapor deposited film with poor coverage laminated on top of 9, 11... After the steps are formed as shown in Figure 3, another absolute MjR film is grown and anisotropically etched, and this is the part of the other insulating film that remains around the steps 1 and 8. 2 figures, 1,000 figures, 3 figures

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の配線パターン形成後、全面に絶縁膜を形成
し、ウェハーに対し垂直にエッチングが進む異方性エッ
チを用い、全面エッチングを行い配線パターン周囲に絶
縁膜を残し、しかる後にその上に他の絶縁膜を成長させ
る工程を有することを特徴とする半導体装置の製造方法
After the wiring pattern of a semiconductor device is formed, an insulating film is formed on the entire surface, and the entire surface is etched using anisotropic etching that proceeds perpendicular to the wafer, leaving an insulating film around the wiring pattern, and then other layers are etched on top of it. 1. A method for manufacturing a semiconductor device, comprising the step of growing an insulating film.
JP13045284A 1984-06-25 1984-06-25 Manufacture of semiconductor device Pending JPS618953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13045284A JPS618953A (en) 1984-06-25 1984-06-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13045284A JPS618953A (en) 1984-06-25 1984-06-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS618953A true JPS618953A (en) 1986-01-16

Family

ID=15034569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13045284A Pending JPS618953A (en) 1984-06-25 1984-06-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS618953A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5737853A (en) * 1980-08-18 1982-03-02 Toshiba Corp Forming method for multilayer thin-film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5737853A (en) * 1980-08-18 1982-03-02 Toshiba Corp Forming method for multilayer thin-film

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