JPS618950A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To implement high density, by constituting interlayer insulating films for the first aluminum wiring and the second aluminum wiring by a silicon oxide film and an upper silicon nitride film. CONSTITUTION:Under the state the first Al wiring pattern is formed, the device is constituted of a semiconductor substrate 31, a field oxide film 32, a gate oxide film 33, a poly-Si gate electrode 34, an interlayer insulating film 35 and a first Al wiring 36. A flat film 37 comprises P-SiO2 having a thickness of 1.2- 2.4mum. Thereafter resist is applied to a thickness of 1-4mum. The entire surface is etched by oxygen plasma. Resist 37' after the etching is embedded in the recess part of a step. Under the state etching is performed at the same time with the P-SiO2, a part of the P-SiO2 is embedded in the recess part of the step of the first Al wiring 36. Then the process called ''etch-back'' is performed. After the etch back, P-SiO2 38a and P-SiN 38b are deposited as interlayer insulating films. The thicknesses of the films of the P-SiO2 and the P-SiN are combined so as not to cause cracks.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly to an integrated circuit having a multilayer wiring structure for the purpose of increasing density.

Conventional Structures and Problems With the increasing density and miniaturization of semiconductor devices, multilayer wiring structures have come into widespread use in microprocessors, memories, gate arrays, and the like. High melting point metal and polycrystalline silicon (hereinafter abbreviated as Poly-8i)
If aluminum is used as the lower layer wiring, heat treatment at about 1000°C is possible, but the sheet resistance is lower than that of aluminum (hereinafter referred to as Aj).
It is abbreviated as 2. ), which is about 1 to 3 orders of magnitude larger, and wiring delay becomes a problem. However, if A2 is used as the lower layer wiring, heat treatment above about 460° C. cannot be performed, and the step coverage and film quality of the interlayer insulating film, as well as hillocks, electromigration, etc., must be taken into consideration.

Next, a conventional example will be explained using figures. Figure 1 shows a MOS using two-layer wiring and a plasma silicon oxide film (hereinafter abbreviated as P8102) as an interlayer insulating film.
) Not applicable when a transistor is configured.

In FIG. 1, a field oxide 12 and a gate oxide 13 are formed on a substrate 11, and a Po1y-8i gate electrode 14 is patterned on these oxides. After that, a CVD5hO2 (silicon oxide film formed by chemical vapor deposition) 15 is deposited as an interlayer insulating film to form a contact hole.Next, a first An interconnect 16 is patterned, and a recess between the AFi interconnects is formed. After a planarizing film 17 is buried for flattening, an interlayer insulating film 18 is deposited and patterned, and then a second AIt interconnect M19 is formed. The planarizing film 17 and the interlayer insulating film 18 are made of P-8102.The problem will be explained with reference to FIG.

(2) Since the film thickness of the first Aj7 wiring is as thick as 0.6 to 1.0 μm, if the second A4 wiring is formed as is, short circuits and disconnections will occur, so it is necessary to flatten it by some method. It is desirable that the planarizing insulating film used here has good step coverage (difference coverage). Plasma silicon nitride film (hereinafter abbreviated as P-5iN) has good step coverage and sufficient breakdown voltage, but since it contains hydrogen, it diffuses into the gate oxide film and causes VT (MO
(S) threshold voltage of transistors). On the other hand, P3102 has poor step coverage and insufficient breakdown voltage. CVD bt02 has a breakdown voltage comparable to P-8iN, but has poor step coverage and AI! , are particularly prone to cracking. There is also a method using plasma oxynitride (hereinafter abbreviated as P-8i ON), but it is difficult to control the film quality.
1) G-P, 1 To ensure interlayer insulation, film type, film thickness, and film quality are important. Particular attention should be paid to hillocks and electromigration. The thicker the film, the higher the resistance to hillocks and electromigration, but the processability during Al-Affi contact formation decreases.
It is usually about 1.0 μm. Although hillocks do not necessarily reduce insulation properties, they tend to cause poor appearance and poor recognition during bonding.

Conventionally, a method of using a composite film as a flattening film and an interlayer insulating film has been known, but this method has the disadvantage of being prone to cracking, so the film type and thickness must be set within a range that does not cause cracks. There is.

Purpose of the Invention The present invention has been made to solve the above-mentioned problems.
The present invention provides an optimal structure for two-layer wiring and a method for forming the same.

Structure of the Invention It was confirmed through experiments that when P-8102 under certain formation conditions was used for an Afi-Afi interlayer film, no hillocks were generated in appearance. This effect is related to the thickness of the P8102 film, and as shown in FIG. 2, the thicker the film, the less hillocks occur, and at 0.5 to 0.7 μm, no hillocks occur at all. However, in terms of interlayer breakdown voltage yield, P 81
02 alone has a lower yield than CV D b 102. Almost the same results are obtained for the two-layer film of P-b 102 and P-3iN. Even in the case of a single layer of P-8iO2, the occurrence of hillocks is the same. This phenomenon does not mean that hillocks no longer occur, but rather that the first AI! Hillocks that occur in the wiring are absorbed by P b iO2 and do not reach the second AQ, but there is no concern that it will cause poor appearance unlike CVD5iO□ or P-8iN.

Sub two C1P', S X O2 (!: CV D
S 102; J) Ruiha P-3102 and P-3iN
By using this two-layer membrane, there will be no appearance of hillocks, and glabellar pressure resistance can be ensured. P-3iNO is more desirable than CV D SiO2 in terms of step coverage, cracking, and moisture resistance.

DESCRIPTION OF EMBODIMENTS FIG. 3 (
-) shows the state in which the first Al wiring pattern has been formed.
These are a gate oxide film 33, a Po1y-8i gate electrode 34, an interlayer insulating film 35, and a first β wiring 36. Figure 3 (b
) shows the state in which the planarization film 37 has been deposited. This flattening film 37 is P-81021, 2 to 2.4μ
It is m. After this, a resist is applied to a thickness of 1 to 4 μm and the entire surface is etched using oxygen plasma, as shown in Fig. 3 (0).
The state shown in is reached.

The etched resist 37' is embedded in the recessed portion of the step. Next, a state in which the resist and P 8102 are simultaneously etched is shown in FIG. 3(d).

A part of P 810237 is embedded in the stepped recess of the first Aft36. The steps shown in FIGS. 3(c) and 3(d) are one glaze process called etchback. Figure 3(e)
After etchback, P-3io2ss is used as an interlayer insulating film.
The state in which al and P-8iN38b are deposited is shown.

The film thickness of P8102 is the 1st AI! , a film thickness of 0.3 to 1.0 μm is required so that the hillocks of , do not reach the 282nd diameter. P-5iN still requires a film thickness of 0.3-1.0 pm to ensure interlayer breakdown voltage. P810
Depending on the combination of film thicknesses of 2 and P-8iN, cracks may occur, but no cracks will occur if the film thickness is within the above range.

FIG. 3(f) shows a state in which a contact hole between An and A1 has been formed. Here, since P-3iN38b is formed by isotropic etching and P-8i 0238a is formed by anisotropic etching, disconnection of No. 2 A4 at the three contact parts does not occur, and an effective film can be formed. It can be easily obtained by using

FIG. 3(q) shows a state where No. 2A(3) is deposited and a battling is formed.

In the above embodiments of the present invention, P-8i O2, P-8iN
We have explained the case using 9-0VD etc.
*';ai=t''8--1-・1a It is effective even if the vertical relationship between P5102 and P-8iN is reversed, but since it involves an etch-back process, it is often used flat) Let's crack raw.

As described in detail, the present invention combines P8102, which does not cause hillocks in appearance, and P-8iN, which has good step coverage and insulation, to create a high-yield method for forming two-layer An interconnects. It can provide structure. Also P
Since bx02 is in the lower layer of P-3iN, it has less influence on semiconductor device characteristics than when only P-3iN is used for the interlayer insulating film.

[Brief explanation of the drawing]

Figure 1 is a schematic cross-sectional view of a conventional two-layer wiring structure, and Figure 2 is a schematic cross-sectional view of a conventional two-layer wiring structure.
Figures 3(a) to 3(q), which are diagrams showing the relationship between the film thickness of S z 02, the interlayer breakdown voltage yield, and the frequency of hillock occurrence, are cross-sectional views of the manufacturing process of a two-layer wiring according to an embodiment of the present invention. be. 36...182nd wiring, 37...Mountain P S
102.38a...P-8iO2,38b ・
-P-3i N, 39-...2nd A4 wiring. Figure 2 P-5:02 o, 7 0.50.40,311), 2
0CVDS:02 0 0.2 0.3
04 QS O, 'T thickness C)〕 Su -

Claims (3)

[Claims] (1) A semiconductor device characterized in that the interlayer insulating film between the first aluminum wiring and the second aluminum wiring is composed of a lower layer of silicon oxide film and an upper layer of silicon nitride film. (2) The semiconductor device according to claim 1, wherein the silicon oxide film is a plasma silicon oxide film and the silicon nitride film is a plasma silicon nitride film. (3) After forming the first aluminum wiring, a step of depositing a first silicon oxide film, a step of spin coating an organic film such as a resist, a step of simultaneously etching the organic film and the first silicon oxide film, a step of depositing a second silicon oxide film and a silicon nitride film, a step of forming a resist pattern and etching the silicon nitride film by causing side etching, and subsequently a step of side etching the second silicon oxide film. 1. A method of manufacturing a semiconductor device, comprising the steps of etching without forming a second aluminum film, and depositing and patterning a second aluminum film.