JPS6188220A - Production of thin film transistor array - Google Patents

Abstract

PURPOSE:To obviate the generation of clouding even if throughput is high by forming successively insulator layers and semiconductor layers under the same conditions for production on not only the front but also rear of a glass substrate then etching the semiconductor layer on the front. CONSTITUTION:A silicon nitride film is formed to 2,500Angstrom as a gate insulating layer 4 on the surface of the glass substrate 1 and an amorphous silicon film is formed to 3,000Angstrom thickness thereon as a semiconductor layer 5. The amorphous silicon is etched to a prescribed pattern by a plasma CVD method and at the same time the semiconductor layer 2' on the rear of the substrate 1 is removed by etching. A mixed soln, composed of hydrofluoric acid:nitric acid: glacial acetic acid = 1:5:15 is used for the etching soln. of the amorphous silicon. The glass substrate is etched and the rear of the substrate is clouded in the conventional process for production using the above-mentioned soln. mixture but the glass substrate is not etched at all and the rear of the substrate is not clouded when the amorphous silicon film is preliminarily formed on the rear of the glass substrate and is simultaneously etched away as in this embodiment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor array used in a liquid crystal display device, and particularly to a method for manufacturing a thin film transistor array using a wet etching method with high throughput.

[Prior art and its problems]

In recent years, with the progress of office automation, the number of pixels of display devices used as man-machine interfaces has been actively increased.

In the field of liquid crystal displays, thin film transistor arrays for switching liquid crystals are being actively developed.

As an example of a conventional method for manufacturing thin film transistor arrays for liquid crystal displays, the method shown in Japanese Patent Application No. 126725/1988 is known. Figures 2 (a) to (h) show the method for manufacturing thin film transistors in order of process. A cross-sectional view is shown.

In this manufacturing method, first, the gate electrode 3 is formed on the surface of the insulating substrate 1 (FIG. 2(a)), and then etched into a predetermined pattern (FIG. 2(b)). Thereafter, a gate insulating layer 4 and a semiconductor layer 5 are formed in the form of a film (FIG. 2(C)).
The semiconductor layer 5 is etched into a predetermined pattern (see FIG.
d)). Next, a metal thin film 6 that will become the drain and source electrodes is formed on the entire upper surface (FIG. 2(e)), and unnecessary parts are etched away by etching, leaving the metal thin film 6 in the area that covers the semiconductor layer 5 that will become the channel. (Fig. 2(f)). Thereafter, a transparent electrode 7 is formed on the entire upper surface (FIG. 2(g)).

Finally, the transparent electrode 7 is turned into a desired pattern by etching, and at the same time the metal thin film 6 on the semiconductor layer 5 serving as a channel is removed to form a drain electrode 8 and a source electrode 9 (see Fig. 2 (h). )) It is preferable that the liquid crystal display panel can be used in both a transmissive type and a reflective type, and since it is inexpensive, an insulating substrate 1 is used.
A glass substrate is usually used.

Further, as the semiconductor layer 5, amorphous silicon or polysilicon is suitable from the viewpoint of transistor characteristics.

Traditional! ! When etching the semiconductor layer 5 by wet etching in the etching method, if the semiconductor layer 5 is made of amorphous silicon or polysilicon, a mixed solution of fluorine and nitric acid is used, so that the glass substrate used as the insulating substrate 1 is also etched. It ends up. Therefore, when a thin film transistor array obtained by the above method is used in a liquid crystal display, a problem arises in that the display quality is significantly degraded. Furthermore, if the back surface of the glass substrate used as the insulating substrate 1 is covered with a resist or the like when wet-etching the semi-S body layer 5, the resist easily peels off and there is a high probability that the glass substrate will be etched. When a resist is applied to the back side, there are problems such as the front surface being easily stained. Note that it is not preferable to use an alkaline solvent for etching amorphous silicon or polysilicon because the uniformity is very poor. On the other hand, if the semiconductor layer 5 is etched by dry etching, the back surface will not be etched, but dry etching has a serious drawback of lower throughput than wet etching.

[Purpose of the invention]

The object of the present invention is to provide a method for manufacturing a thin film transistor array with good throughput and display quality by eliminating these conventional drawbacks.

[Structure of the invention]

The present invention provides a method for manufacturing a thin film transistor array in which a glass substrate is used as an insulating substrate, at least an insulating layer and a semiconductor layer are sequentially formed on the surface thereof, and only the semiconductor layer is subjected to a pattern etching process. This method of manufacturing a thin film transistor array is characterized in that an insulator layer and a semiconductor layer are sequentially formed under the same manufacturing conditions, and then the semiconductor layer on the surface is etched.

[Detailed explanation of configuration]

The present invention has solved the problems of the prior art by adopting the above-described configuration. The method for manufacturing a thin film transistor array according to the present invention will be explained below with reference to FIGS. 1(a) to 1(h) showing the process order. First, a glass substrate is used as the insulating substrate 1, an insulating layer 2 and a semiconductor layer 2' are sequentially formed on the back surface of the insulating substrate 1, and a gate electrode 3 is formed on the front surface of the insulating substrate 1 (see FIG. 1(a).
)). Next, the gate electrode 3 is etched into a predetermined pattern (FIG. 1(b)), and then a gate insulator layer 4 and a semiconductor layer 5 are sequentially formed thereon in the form of a film (FIG. 1(C)).
At the same time as etching the semiconductor layer 5 into a predetermined pattern, the semiconductor layer τ on the back surface of the insulating substrate 1 is removed (FIG. 1(d)
)).

On the other hand, a metal thin film 6 that will become the drain and source electrodes is formed on the entire surface of the insulating substrate 1 (FIG. 1(e)), and unnecessary parts are etched, leaving the metal thin film 6 only in the part that covers the semiconductor layer 5 that will become the channel. (Fig. 1(f))
) Subsequently, a transparent electrode 7 is patterned on the entire surface in a desired pattern (FIG. 1(g)), and at the same time, the metal thin film 6t on the semiconductor layer 5 serving as a channel is removed, and a drain electrode 8 and a source electrode 9 are formed. (Fig. 1(h)).

Therefore, in FIG. 1(d), even if the semiconductor layer 5 is etched into a predetermined pattern and the semiconductor layer 2 on the back surface is simultaneously etched by wet etching, the glass substrate serving as the insulating substrate 1 is not etched.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to FIGS. 1(a) to (h). First, titanium 100A was deposited as a metal for the genit electrode on a glass substrate l on which a silicon nitride film with a thickness of 250 OA as an insulating layer 2 and an amorphous silicon film as a semiconductor layer 2 with a thickness of 300 OA were successively formed on the back surface by plasma CVD. (a)) and etched into a predetermined pattern by a photoresist method (FIG. 1(b)). In addition, for etching titanium, hydrofluoric acid:nitric acid:water=i:t:1o.

However, the glass substrate was hardly etched by this etching solution. Then glass substrate 1
Silicon nitride film 6250 as gate insulating layer 4 on the surface of
OA, an amorphous silicon film is used as the semiconductor layer 5.
The amorphous silicon is continuously formed to a thickness of 0 OA using the plasma method (Fig. 1 (C)), and at the same time, the amorphous silicon is etched into a predetermined pattern using the photoresist method, and at the same time, the semiconductor layer 2' on the back surface of the glass substrate 1 is removed by etching. (Figure 2(d)). The etching solution for amorphous silicon is hydrofluoric acid: nitric acid: glacial acetic acid = 1:5.
: A mixed solution of 15 was used. In the conventional manufacturing method using this mixed solution, the glass substrate was etched and clouding occurred on the back surface, but when an amorphous silicon film is also formed on the back surface of the glass substrate 1 and removed by etching at the same time as in this example, The glass substrate 1 was not etched at all, so no clouding occurred.

This is because a silicon nitride film is formed under the amorphous silicon film on the back surface as well as the front surface, and the etching rate of this film is sufficiently slower than that of the amorphous silicon film. After that, titanium is automatically formed on the entire upper surface as a metal thin film 6 that will become the drain and source electrodes (FIG. 1(e)), and unnecessary parts are removed by etching, leaving a thin gold film 6 that covers the semiconductor layer 5 that will become the channel. (Figure 1(f)
), the same etching solution as that for the titanium of the gate electrode was used. After that, transparent electrode 7 is placed on the entire top surface.
The transparent electrode 7 was formed to a thickness of 150 OA using the ITOt-argon sputtering method (FIG. 1(g)), and the metal thin film 6 on the semiconductor layer 5 as a channel was removed at the same time as the transparent electrode 7 was patterned into a desired pattern using the photoresist method. , a drain electrode 8 and a source electrode 9 were formed (FIG. 1(h)). ITO etching solution contains hydrochloric acid:water = 1:l
A mixture of these was used. The glass substrate was not etched at all by the ITO etching solution.

〔Effect of the invention〕

As described above, if the method for manufacturing a thin film transistor according to the present invention is used, the insulating layer and the semiconductor layer are sequentially formed on the back surface of the glass substrate, so even if a wet etching method with good throughput is used, the glass substrate will be etched and clouding will occur. Therefore, it is possible to provide a method for manufacturing a thin film transistor array with high throughput and good display quality on a liquid crystal display.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are cross-sectional views showing the manufacturing process of a thin film transistor array according to the present invention, and FIGS. 2(a) to (h) are cross-sectional views showing the manufacturing process of a conventional thin film transistor array. l...Insulating substrate, 2...Insulator layer,! ... Semiconductor layer, 3... Gate electrode, 4... Gate insulator layer, 5
... Semiconductor layer, 6... Gold serving as drain and source electrodes [4 copies, 7...° transparent electrode, 8... Drain electrode, 9... Source electrode

Claims (1)

[Claims] (1) In a method for manufacturing a thin film transistor array in which a glass substrate is used as an insulating substrate, at least an insulating layer and a semiconductor layer are sequentially formed on the surface thereof, and pattern etching is performed only on the semiconductor layer, the same process is performed on the back surface of the glass substrate. 1. A method for manufacturing a thin film transistor array, comprising sequentially forming an insulator layer and a semiconductor layer under manufacturing conditions, and then etching the semiconductor layer on the surface.