JPS618788A - Memory control system - Google Patents

Abstract

PURPOSE:To read and write data in and out of the memory at a high speed by controlling the generation timining of a data strobe signal according to the delay time of carry signals of cascaded address counter elements. CONSTITUTION:The cascaded address elements CNTR1-CNTR6 of an address counter 2 calculate an address consisting of, for example, four bits in response to an increment signal from a control circuit 3 to access the memory 1 with a 24-bit address. If the element CNTR3 among the elements CNTR1-CNTR6 does not generate a carry signal CY3, the circuit 3 generates a strobe signal STB after the generation of the signal INC by estimating a delay time T0 three times as long as a delay time T0 due to the generation of the carry signal among the elements CNTR1-CNTR3. On the other hand, a time 5T0 which is 5 times is estimated for a signal STB only when the signal CY3 is generated. Conseqently, data are read out of and written in the memory at a high speed without affected wholly by the delay of the carry signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory address control, and more particularly to a memory control system when a plurality of l-chip memory address counters are connected in cascade.

Traditionally, when controlling the address of a large-capacity memory such as a dictionary memory in OCR, the address signal is around 20 pips. For block (1), counter elements C-NTR each having about 4 bits in one chip are connected in cascade for 5 or 6 chips depending on the number of bits of the memory address to perform address control.

With such a configuration, each counter element CNTR
It takes time for the carry signal CY to propagate between the chips, and the proximity of the carry signal CY accumulates accordingly.
Therefore, as shown in FIG. 7, after the memory 1 is accessed/entered, the address counter 2 consisting of each counter element column increments by 1 bit, that is, the time T required to complete the increment 1 (address uncertainty period). It is necessary to determine the cycle for reading data in the memory (2), taking into account the following: In the figure, ADDRES is an address signal and indicates a state of change with respect to the data strobe signal. Further, Tacc indicates memory access time. Note that the data strobe signal ST
At the rising edge of B, the address counter 2 consisting of each counter element column is incremented by one bit.

However, when a large capacity memory 1 is accessed continuously, such as in an OCR dictionary search, the increase in processing time due to the above-mentioned time T cannot be ignored, and the data stored in the large capacity memory 1 cannot be ignored. (reading or writing data) cannot be performed at high speed.

And fish The present invention has been made in consideration of the above points.

When performing memory address control by cascading multiple counter elements that are made into one chip for multiple bits according to the number of bits of the memory address, reading and writing data to the memory is carried between the chips of each counter element. The present invention provides a memory control method that enables high-speed operation without being affected by signal delays.

In order to achieve the object, the present invention cascades a plurality of counter elements for multiple bits on one chip according to the number of bits of a memory address to perform memory address control. The output carry signal is detected, and the time interval from the output of the increment 1 signal to the output of the data strobe signal is variably controlled in an address counter consisting of a counter element array according to the delayed dark part of the carry signal at that time. This is to encourage them to take measures.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

To simplify the explanation, as shown in Figure 1, the number of address bits of memory (memory block) 1 is assumed to be 24 bits, and six 4-bit TC counter elements CNTR are connected in cascade per chip. Let me explain what happens when I do this. In this case, if the delay time required for the propagation of the carry signal between each counter element CNTR is To, then a carry delay time of 5 To occurs in the entire address counter 2 whose counter element row is r%. Note that the TO is normally about 10n5ec, and in that case the total carry delay time T is 50nSe
It will be about c.

In this configuration, the third counter element CNT
Focusing on R3, unless the carry signal CY3 is output from the counter element CNTR3, each of the fourth to sixth counter elements CNTR4 to CNT from the next stage onwards
The contents of R6 do not change. That is, at that time, the carry delay time 2To between the counter elements CNTR4 to CNTR6 does not occur. Therefore, at that time, the address counter as a whole must perform an operation that takes into account only the carry delay time 3To between the counter elements CNTRI to CNTR3. It's a good thing. Furthermore, when the carry signals C and Y3 are output from the third counter element CNTR3, it is only necessary to cause the address counter as a whole to perform an operation that allows for a carry delay time of 5 to 0 minutes only when the carry signal CY is generated. become.

Now, the increment signal IN output from the control circuit 3
The address counter 2 is incremented by G, and all 4 bits 1 to 1 in the counter element CNTR3 are II i p)
, the carry signal CY3 is output from the counter element CNTR3. However, in the next cycle, the contents of the next stage counter elements CNTR4 to CNTR6 change, so the control circuit 3 outputs the carry signal CY3 from the counter element CNTR3. It reads the signal CY3 and detects that the contents are all #I II, and accordingly changes the strobe signal STB, which takes in the data read from the memory 1 into the buffer register 4, to the increment signal I.
The output is delayed by 3To from the NC.

FIG. 2 shows the timing of each part's operation at that time. In the figure, CLK indicates a control clock in the control circuit 3. In addition, Fig. 3 shows the control circuit 3 at that time.
It shows the state transition in . In the figure, SO to S6 indicate states, which change at the cycle of clock CLK. Among each state, SO is the generation cycle of the strobe, S2 is the cycle for determining the presence or absence of the carry signal CY3, and 83 to S4 are the cycles for determining the presence or absence of the carry signal CY3.
Each cycle for the delay operation of To is shown.

Note that in the following explanation, the output of the carry signal CY3 from the counter element CNTR3 is detected and the strobe signal STB is delayed by 3To. It goes without saying that the strobe signal STB may be delayed by a predetermined value depending on the position of the counter element detected.

FIG. 4 shows another embodiment of the present invention, in which each carry signal CY, 1°C, Y2 . CY3
are read into the control circuit 3, and the counter element CN
When it is detected that the carry signal CY1 is output from T R'1, 1. T.

The strobe signal STB delayed by 2T is applied to the buffer register 4, and when it is detected that the carry signal CY2 is output from the counter element CNTR,2,
The strobe signal STB delayed by o minutes is applied to the buffer register 4, and the carry signal CY3 is output from the counter element CNTR3.
More precise control such as applying the lobe signal STB to the buffer register 4 delayed by o minutes is performed. FIG. 5 shows the state transition in the control circuit 3 at that time.

As described above, in the memory control method according to the present invention, the address counter is configured by cascading the counter elements integrated into one chip, and the address counter due to the delay of the carry signal between each counter element. The first advantage is that it is possible to prevent a decrease in the operating speed of the counter, and it is possible to read and write data to and from the memory at high speed without being affected by the delay of the carry signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a system configuration for concretely implementing the memory control method according to the present invention, FIG. 2 is a time chart 1-1 showing the timing of operation of each part in the same embodiment, and FIG. A diagram showing the state transition in the control circuit at that time, FIG. 4 is a block diagram showing another system configuration example for concretely implementing the memory control method according to the present invention, and FIG. 5 is a control circuit of the same embodiment. FIG. 6 is a diagram showing a general address counter of a memory consisting of a row of counter elements integrated into one chip.
FIG. 7 is a time chart showing changes in the state of the address signal with respect to the data strobe signal in the configuration of FIG. 6. 1...Memory 2...Address counter 3...
Control circuit 4... Buffer register Figure 1' Mac Figure 2

Claims (1)

[Claims] 1 of multiple bits depending on the number of bits of memory address
When controlling memory addresses by cascading a plurality of chipped counter elements, there is a means for detecting the carry signal output from the counter elements, and a means for detecting the carry signal output from the counter element array according to the delay time of the detected carry signal. A memory control method that takes means to variably control the time interval from when an increment signal is issued to an address counter until a data strobe signal is issued.