JPS618786A - メモリ制御方式 - Google Patents

メモリ制御方式

Info

Publication number
JPS618786A
JPS618786A JP59127826A JP12782684A JPS618786A JP S618786 A JPS618786 A JP S618786A JP 59127826 A JP59127826 A JP 59127826A JP 12782684 A JP12782684 A JP 12782684A JP S618786 A JPS618786 A JP S618786A
Authority
JP
Japan
Prior art keywords
data
write
read
rams
scan chain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59127826A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0150036B2 (enExample
Inventor
Yukinori Matsukawa
幸徳 松川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59127826A priority Critical patent/JPS618786A/ja
Publication of JPS618786A publication Critical patent/JPS618786A/ja
Publication of JPH0150036B2 publication Critical patent/JPH0150036B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP59127826A 1984-06-21 1984-06-21 メモリ制御方式 Granted JPS618786A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59127826A JPS618786A (ja) 1984-06-21 1984-06-21 メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59127826A JPS618786A (ja) 1984-06-21 1984-06-21 メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS618786A true JPS618786A (ja) 1986-01-16
JPH0150036B2 JPH0150036B2 (enExample) 1989-10-26

Family

ID=14969623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59127826A Granted JPS618786A (ja) 1984-06-21 1984-06-21 メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS618786A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205815B2 (en) 2003-11-25 2007-04-17 Samsung Electronics Co., Ltd. Method and integrated circuit apparatus for reducing simultaneously switching output

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205815B2 (en) 2003-11-25 2007-04-17 Samsung Electronics Co., Ltd. Method and integrated circuit apparatus for reducing simultaneously switching output

Also Published As

Publication number Publication date
JPH0150036B2 (enExample) 1989-10-26

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