JPS6179544U - - Google Patents
Info
- Publication number
- JPS6179544U JPS6179544U JP16323884U JP16323884U JPS6179544U JP S6179544 U JPS6179544 U JP S6179544U JP 16323884 U JP16323884 U JP 16323884U JP 16323884 U JP16323884 U JP 16323884U JP S6179544 U JPS6179544 U JP S6179544U
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- region
- bonding pad
- capacitance generated
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 5
- 239000011229 interlayer Substances 0.000 claims 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図ａ〜ｃは本考案の一実施例の拡散系の平
面図、Ａ−Ａ′断面図、Ｂ−Ｂ′断面図、第２図
ａ〜ｃは本考案の一実施例の配線系の平面図、Ｃ
−Ｃ′断面図、Ｄ−Ｄ′断面図である。
１…Ｐ型半導体基板、２…Ｎ型埋込領域、３…
Ｎ型領域、４…Ｐ型領域、５，６…Ｎ型領域、７
…コンタクト、８…第１の絶縁膜、９，９′…第
１の導電層、１０…コンタクト、１１…第２の絶
縁膜、１２…第２の導電層。
Figures 1 a to c are plan views of a diffusion system according to an embodiment of the present invention, A-A' sectional views, and B-B' sectional views, and Figures 2 a to c are wiring systems of an embodiment of the present invention. Plan view of C.
-C' sectional view and DD' sectional view. 1... P-type semiconductor substrate, 2... N-type buried region, 3...
N-type region, 4...P-type region, 5, 6...N-type region, 7
... Contact, 8... First insulating film, 9, 9'... First conductive layer, 10... Contact, 11... Second insulating film, 12... Second conductive layer.
Claims (1)
域に複数のエミツタ領域を有するトランジスタ構
造の拡散領域を設け、その上に層間絶縁膜を介し
て絶縁された二つの部分から成る導電層を少くと
も一層設け、該導電層の一方の部分を前記エミツ
タ領域に選択的に接続の他方の部分をベース領域
に選択的に接続し、前記導電層の上に絶縁膜を介
してボンデイングパツドを設け、前記トランジス
タ構造の拡散領域に生成されるＰＮ接合容量と、
前記拡散領域と前記導電層との間に生成される容
量と、前記導電層と前記ボンデイングパツドとの
間に生成される容量とをすべて並列に接続したこ
とを特徴とする半導体装置。 A diffusion region of a transistor structure having a plurality of emitter regions is provided in a region of a semiconductor substrate where a bonding pad is to be formed, and at least one conductive layer consisting of two parts insulated via an interlayer insulating film is provided thereon; One part of the conductive layer is selectively connected to the emitter region and the other part is selectively connected to the base region, a bonding pad is provided on the conductive layer via an insulating film, and the transistor structure is PN junction capacitance generated in the diffusion region of
A semiconductor device characterized in that a capacitance generated between the diffusion region and the conductive layer and a capacitance generated between the conductive layer and the bonding pad are all connected in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16323884U JPH0419808Y2 (en) | 1984-10-29 | 1984-10-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16323884U JPH0419808Y2 (en) | 1984-10-29 | 1984-10-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6179544U true JPS6179544U (en) | 1986-05-27 |
| JPH0419808Y2 JPH0419808Y2 (en) | 1992-05-06 |
Family
ID=30721098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16323884U Expired JPH0419808Y2 (en) | 1984-10-29 | 1984-10-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0419808Y2 (en) |
-
1984
- 1984-10-29 JP JP16323884U patent/JPH0419808Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0419808Y2 (en) | 1992-05-06 |
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