JPS6179540U - - Google Patents
Info
- Publication number
- JPS6179540U JPS6179540U JP1984163273U JP16327384U JPS6179540U JP S6179540 U JPS6179540 U JP S6179540U JP 1984163273 U JP1984163273 U JP 1984163273U JP 16327384 U JP16327384 U JP 16327384U JP S6179540 U JPS6179540 U JP S6179540U
- Authority
- JP
- Japan
- Prior art keywords
- stage
- semiconductor chip
- inner leads
- frame
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000011521 glass Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本発明実施例の平面図、第２図は第１
図の固定枠体を用いた半導体パツケージの断面図
、第３図は固定枠体とインナーリードの接着部分
の一部の拡大断面図、第４図は従来の半導体パツ
ケージの断面図、第５図は従来のインナーリード
保持部材を示すリードフレームの一聞の平面図で
ある。 図中、１１はインナーリード、１２は半導体チ
ツプ、１３はステージ、１４は固定枠体、１４ａ
は凹部、１５は低融点ガラス、１６は樹脂、をそ
れぞれ示す。
図の固定枠体を用いた半導体パツケージの断面図
、第３図は固定枠体とインナーリードの接着部分
の一部の拡大断面図、第４図は従来の半導体パツ
ケージの断面図、第５図は従来のインナーリード
保持部材を示すリードフレームの一聞の平面図で
ある。 図中、１１はインナーリード、１２は半導体チ
ツプ、１３はステージ、１４は固定枠体、１４ａ
は凹部、１５は低融点ガラス、１６は樹脂、をそ
れぞれ示す。
Claims (1)
- 半導体チツプと、該半導体チツプが接着された
ステージと、その周りに延在して設けられた複数
のインナーリードと、該インナーリードを上下か
ら挾んでなる枠体とを有し、該枠体の表面に複数
の凹部または凸部が設けられ、前記半導体チツプ
と前記ステージと前記複数のインナーリードと前
記枠体とが樹脂封止されてなることを特徴とする
半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984163273U JPS6179540U (ja) | 1984-10-29 | 1984-10-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984163273U JPS6179540U (ja) | 1984-10-29 | 1984-10-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6179540U true JPS6179540U (ja) | 1986-05-27 |
Family
ID=30721131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984163273U Pending JPS6179540U (ja) | 1984-10-29 | 1984-10-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6179540U (ja) |
-
1984
- 1984-10-29 JP JP1984163273U patent/JPS6179540U/ja active Pending