JPS6177420A - Phase comparator circuit - Google Patents

Abstract

PURPOSE:To attain ease of circuit integration by combining two FF circuits and three gate circuits so as to form a phase comparator circuit thereby eliminating the need for a time constant circuit. CONSTITUTION:An output of an FF13 to which an input signal is fed is applied to an FF14. The input to the FFs13, 14 is latched by a clock signal fed to its clock terminal 12 at the same time. Then an output of the FF13 and the input signal are added by an EOR circuit 15 and outputs of the FFs13, 14 are added by an EOR circuit 16. Further, the output of the EOR circuit 16 and signal obtained by inverting the clock signal at an inverter 18 are processed logically at an AND circuit 17. Then a phase error signal between the input signal and the clock signal is obtained between the outputs of the EOR circuit 15 and the AND circuit 17. In forming the phase comparator circuit in this way, no time constant circuit is required and then ease of circuit integration is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention applies EFM (Eighth t
o Fourteen Modulation) The present invention relates to a phase comparator circuit suitable for use in a PLL circuit or the like that demodulates a clock signal from a modulated wave.

[Conventional technology]

As a phase comparator circuit used in a PLL circuit that demodulates a clock signal from an EFM modulated wave, a circuit as shown in FIG. 3 has conventionally been used.

That is, in the figure, (1) is an input terminal to which an EFM signal wave is supplied as an input signal, and (2) is a clock terminal to which a reference clock signal is supplied, and the input from input terminal (1) is The signal is delayed by a predetermined amount in a delay circuit (3), for example, by T/2, where T is the period of the clock signal applied to the clock terminal (2), and is then passed through an exclusive OR circuit (hereinafter referred to as an EOR circuit) (4). is supplied to one input terminal of the EOR circuit (4), and directly supplied to the other input terminal of the EOR circuit (4). The output of the EOR circuit (4) is sent to another EOR circuit (5).
), the clock signal from the clock terminal (2) is supplied to the other input terminal of this EOR circuit (5), and the clock signal from the output terminal (6) of the EOR circuit (5) is supplied to the other input terminal of the EOR circuit (5). ) is retrieved.

Now, from the input terminal (1), the EFM shown in Figure 4A is
When the input signal Sl, which is a signal, is supplied to the delay circuit (3), this signal S1 is delayed by T/2 here, and the signal S1 is delayed by T/2 as shown in FIG.
The signal is extracted as a signal S2 as shown in FIG. This signal S
2 is supplied to one input terminal of the EOR circuit (4), and here the input terminal (1
1 is added to the signal S1 supplied from CK1, so that a signal S3 as shown in FIG. 4CK is obtained on the output side. This signal S3 is supplied to one input terminal of the EOR circuit (5), and the lock signal shown in FIG. S4 and a signal S5 as shown in FIG. 4E is obtained on the output side.

The signal S5 obtained in FIG. 4E indicates that the input signal S1 and the clock signal S4 are in phase agreement.
Incidentally, if the input signal S1 lags behind the clock signal S4 (shifts to the right in the drawing), the high level period of the signal S5 becomes shorter; (shifting to the left), the high level period of the signal S5 increases. In this way, the phase error signal is detected.

[Problem that the invention seeks to solve]

By the way, in the case of the conventional circuit having the configuration as shown in Fig. 3, a delay circuit (3) is provided to delay the input signal by a predetermined amount, so a time constant circuit is required for this purpose, so it is not suitable for IC implementation. There is an inconvenience.

The present invention has been made in view of these points, and provides a phase comparator circuit that can be integrated into an IC.

[Means for solving problems]

This invention comprises a first flip-flop circuit a3 to which an input signal is supplied, a second flip-flop circuit I to which an output of this flip-flop circuit is supplied, and a link between the input signal and the flip-flop circuit @1. A first gate circuit a9 to which an output is supplied and 1. A second ?? to which the outputs of the first and second flip-flop circuits are supplied. -) circuit (161) and a third gate circuit (171) to which the output of this gate circuit and the clock signal applied to the first and second flip-flop circuits are supplied, A phase error signal between the input signal and the clock signal is obtained between the gate circuit and the third gate circuit.

[Effect]

For example, an EFM signal is supplied as an input signal to the first flip-flop circuit a3, and the output of the first flip-flop circuit a3 is sent to the second flip-flop circuit (14)K.
supply The inputs of the first and second flip-flop circuits are simultaneously latched by a clock signal supplied to its clock terminal σ2. The first flip-flop circuit (13 outputs and input signals are connected to the E
The OR circuit α9 adds the sum, and the first flip-flop circuit (
13 and the output of the second flip-flop circuit a4) are added by an EOR circuit a9 serving as a second gate circuit. Further, the output of the KEOR circuit αe and the signal obtained by inverting the clock signal at the inverter circuit (18) are logically processed by an AND circuit αη serving as a third r-to circuit. Then, a phase error signal between the input signal and the clock signal is obtained between the EOR circuit (151) and each output side of the AND circuit αη.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail based on FIGS. 1 and 2.

FIG. 1 shows the circuit configuration of this embodiment. In the figure, (111 is an input terminal to which an input signal such as an EFM signal is supplied, and (L21 is a clock terminal to which a reference clock signal is supplied. The input terminal (111) is connected to the input terminal of the first flip-flop circuit 00A, and the clock terminal α2 is connected to the clock terminal CKK of the 7-rip 7a-tube circuit σJ. input terminal (FJ' from 111)
The M signal is latched into flip-flop circuit 03.

The output terminal Q of the flip-flop circuit (13) is connected to the input terminal DK of the second flip-flop circuit f141, and the clock terminal CK of the flip-flop circuit I is connected to the clock terminal α2. is supplied, the output of the flip-flop circuit (131) is latched into the flip-flop circuit I.The input terminal u11 and the output terminal Q of the flip-flop circuit I are connected to each input terminal of the EOR circuit a9 as the first gate circuit. is connected to the flip-flop circuit (13, (
14) Each output terminal Q of EO serves as a second gate circuit.
R circuit (connected to each input terminal of 1e.

The output side of the EOROR circuit is connected to one input terminal of an AND circuit αη serving as a third gate circuit, and the clock terminal α2 is connected to the other input terminal of this AND circuit (17) via an inverter αg.

The output side of the FOR circuit (15) is connected to an active element such as a P-channel MO8FET σ9 via an inverter (La).
- and the output side of the AND circuit αD is connected to the gate terminal of another active element, such as an N-channel type MO8FETC21. Then, the source terminal of FEl'J and the drain terminal of FBT (21) are interconnected, and the output terminal (211) is derived from the connection point.
The drain terminal of FET (19) is connected to the positive power supply terminal (10B), and the source terminal of FET (2) is grounded.

Next, the operation of this circuit will be explained with reference to the signal waveforms shown in FIG.

Now, when a gFM signal S1 as shown in FIG. 2 AK is supplied from the input terminal αυ to the input terminal DK of the flip-flop circuit 0, this signal S1 is output from the clock terminal AK in FIG.
As a result, an output signal S3 as shown in FIG. 2C is obtained on the output terminal Q side of the flip-flop circuit (13). The signal is supplied to the input terminal of the flip-flop circuit I and is clocked by the clock signal S2.As a result, an output signal S4 as shown in FIG. 2DK is obtained at the output terminal Q side of the flip-flop circuit I.

Furthermore, the EFM signal S1 from the input terminal αυ and the output signal S3 from the flip-flop circuit a3 are connected to the EOR circuit (15
1, and an output signal S5 as shown in FIG. 2H is obtained at its output side. Also, flip-flop circuit 0 and (
14) (7) Each output signal s3. S4 is the EOR circuit (lG
K is supplied, and an output signal S6 as shown in FIG. 2H is obtained on the output side. This output signal S6 is the AND circuit αD
The clock signal S2 from the clock terminal α2 is inverted by an inverter (181) and supplied to the other input terminal of the clock terminal α2.As a result, the output side of the AND circuit t171 is The output signal S as shown in
7 is obtained.

The output signal S5 of the EOR circuit (151 is inverted by the inverter αε and supplied to the gate terminal of the FET (1!1), and the output signal S7 of the AND circuit (171 is directly supplied to the gate terminal of the FET (2υ). On the output terminal Ca1l side, there are 3-states (5states) as shown in FIG. 2H.
) is derived. In FIG. 2H, the broken line indicates a state with no potential (FET(19,
1) represents the pinch-off voltage state). and,
In FIG. 2H, during the period t1, the phase of the EFM signal S1 matches the phase of the clock signal S2, and during the period t2, the EFM signal S1 is delayed by a predetermined amount with respect to the clock signal S2. , during the period t3, the EFM signal S1
shows a state in which the clock signal 82 is ahead of the clock signal 82 by a predetermined amount.

In this way, phase comparison is substantially performed only at the nip portion of the EFM signal, which is the input signal, and phase comparison is possible even when the signal is not a continuous signal, and a phase comparison circuit can be constructed without using a time constant. Note that in the above embodiment, the output terminal Qυ
Although the output signal S8 obtained on the side is 3-state, it is also possible to set the value at the off time to the midpoint potential. Moreover, although the input signal is an EFM signal in the above description, it is not limited to this, and other signals may be used. The first, second, and third gate circuits are not limited to the EOFL circuit and the AND circuit, but may be other logic circuits as long as similar effects can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, an input signal is sequentially taken into the first and second flip-flop circuits according to a clock signal, and the input signal and the output of the first flip-flop circuit are
The outputs of the first and second flip-flop circuits are supplied to a first gate circuit such as an OR circuit, the outputs of the first and second flip-flop circuits are supplied to a second gate circuit such as an EOR circuit, and the outputs of the second gate circuit and the above-mentioned clock are supplied. Since the phase error signal is supplied to the output side of the first and third gate circuits, a conventional time constant circuit is not required, and the phase comparison circuit can be easily integrated into an IC. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a circuit configuration diagram showing an example of a conventional circuit, and FIG. This figure is a signal waveform diagram for explaining the operation of FIG. 3.

Claims (1)

[Claims] 1. A first flip-flop circuit to which an input signal is supplied, a second flip-flop circuit to which an output of the flip-flop circuit is supplied, and the input signal and the first flip-flop circuit. a first gate circuit to which the output of the circuit is supplied; a second gate circuit to which the outputs of the first and second flip-flop circuits are supplied; a third gate circuit to which a clock signal applied to the flip-flop circuit is supplied, and a phase error signal between the input signal and the clock signal is provided between the first gate circuit and the third gate circuit. A phase comparator circuit characterized in that it obtains the following. 2. The phase comparator circuit according to claim 1, wherein exclusive OR circuits are used as the first and second gate circuits, and an AND circuit is used as the third gate circuit.