JPS6176928U - - Google Patents
Info
- Publication number
- JPS6176928U JPS6176928U JP16203184U JP16203184U JPS6176928U JP S6176928 U JPS6176928 U JP S6176928U JP 16203184 U JP16203184 U JP 16203184U JP 16203184 U JP16203184 U JP 16203184U JP S6176928 U JPS6176928 U JP S6176928U
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- hole
- magnetic layer
- layer
- magnetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 11
- 230000003014 reinforcing effect Effects 0.000 claims description 5
- 239000000696 magnetic material Substances 0.000 claims 3
- 238000002788 crimping Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Description
第１図はこの考案の一実施例の分解斜視図であ
る。第２図は第１図の線−における断面図で
ある。第３図は磁性体層とその主面に形成された
第１および第２の補強用導体パターンとを表す斜
視図である。第４図ないし第６図は第１図および
第２図に示すチツプ形インダクタのスルーホール
部分における導体パターンの１つの接続例を示し
、第４図は圧着前のその要部断面図であり、第５
図は第４図の要部斜視図であり、第６図は圧着後
のその要部断面図である。第７図はチツプ形イン
ダクタ全体を示す斜視図である。第８図は第７図
の線−における断面図である。第９図および
第１０図は従来のチツプ形インダクタを示す図で
あり、第９図はその要部分解斜視図であり、第１
０図はスルーホール部分における接続を示す要部
断面図である。
図において、１０はチツプ形インダクタ、１１
〜１８は磁性体層、１３ａ〜１６ａはスルーホー
ル、１２ｂ〜１６ｂは導体パターン、１３ｃ〜１
６ｃは第１の補強用導体パターン、１４ｄ〜１７
ｄは第２の補強用導体パターンを示す。
FIG. 1 is an exploded perspective view of one embodiment of this invention. FIG. 2 is a sectional view taken along the line - in FIG. 1. FIG. 3 is a perspective view showing the magnetic layer and first and second reinforcing conductor patterns formed on the main surface thereof. 4 to 6 show one example of connection of the conductor pattern in the through-hole portion of the chip-type inductor shown in FIGS. 1 and 2, and FIG. 4 is a sectional view of the main part thereof before crimping, Fifth
This figure is a perspective view of the main part of FIG. 4, and FIG. 6 is a sectional view of the main part after crimping. FIG. 7 is a perspective view showing the entire chip-type inductor. FIG. 8 is a sectional view taken along the line - in FIG. 7. 9 and 10 are diagrams showing a conventional chip-type inductor, and FIG. 9 is an exploded perspective view of the main part thereof.
Figure 0 is a sectional view of the main part showing the connection in the through-hole portion. In the figure, 10 is a chip type inductor, 11
-18 are magnetic layers, 13a-16a are through holes, 12b-16b are conductive patterns, 13c-1
6c is the first reinforcing conductor pattern, 14d to 17
d indicates the second reinforcing conductor pattern.
Claims (1)
する２つの磁性体層のそれぞれの上面に導体パタ
ーンが形成され、上の磁性体層には下の磁性体層
と積層された状態でこの下の磁性体層に形成され
た前記導体パターンに対応する位置にスルーホー
ルが形成され、前記上の磁性体層に形成された前
記導体パターンはこのスルーホールの内周面に延
びて形成され、前記２つの磁性体層が積層された
とき前記スルーホールを通して下の磁性体層の導
体パターンと上の磁性体層の導体パターンとが接
続されるチツプ形インダクタにおいて、 前記上の磁性体層の下面であつて前記スルーホ
ールの周縁に形成され、かつ前記スルーホールを
通してその上面に形成された前記導体パターンに
接続される第１の補強用導体パターン、および 前記上の磁性体層の上にさらに積層される磁性
体層の下面であつて前記上の磁性体層の前記スル
ーホールの位置に対応して形成される第２の補強
用導体パターンを含むことを特徴とする、チツプ
形インダクタ。[Claims for Utility Model Registration] It includes a plurality of laminated magnetic layers, and a conductive pattern is formed on the upper surface of each of two vertically adjacent magnetic layers, and the upper magnetic layer has a lower magnetic layer. A through hole is formed at a position corresponding to the conductor pattern formed in the lower magnetic layer in a laminated state with the upper magnetic layer, and the conductor pattern formed in the upper magnetic layer is inserted into the through hole. In a chip-shaped inductor that is formed to extend around the circumferential surface, and when the two magnetic layers are laminated, the conductor pattern of the lower magnetic layer and the conductor pattern of the upper magnetic layer are connected through the through hole, a first reinforcing conductor pattern formed on the lower surface of the upper magnetic layer at the periphery of the through hole and connected to the conductor pattern formed on the upper surface through the through hole; It is characterized by including a second reinforcing conductor pattern formed on the lower surface of the magnetic material layer further laminated on the magnetic material layer and corresponding to the position of the through hole in the upper magnetic material layer. chip type inductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16203184U JPS6176928U (en) | 1984-10-25 | 1984-10-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16203184U JPS6176928U (en) | 1984-10-25 | 1984-10-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6176928U true JPS6176928U (en) | 1986-05-23 |
Family
ID=30719927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16203184U Pending JPS6176928U (en) | 1984-10-25 | 1984-10-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6176928U (en) |
-
1984
- 1984-10-25 JP JP16203184U patent/JPS6176928U/ja active Pending
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