JPS59145009U - Laminated chip coil - Google Patents

Laminated chip coil

Info

Publication number
JPS59145009U
JPS59145009U JP3787783U JP3787783U JPS59145009U JP S59145009 U JPS59145009 U JP S59145009U JP 3787783 U JP3787783 U JP 3787783U JP 3787783 U JP3787783 U JP 3787783U JP S59145009 U JPS59145009 U JP S59145009U
Authority
JP
Japan
Prior art keywords
chip coil
laminated chip
coil
multilayer chip
magnetic layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3787783U
Other languages
Japanese (ja)
Inventor
治文 万代
伴野　国三郎
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP3787783U priority Critical patent/JPS59145009U/en
Publication of JPS59145009U publication Critical patent/JPS59145009U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の興味ある先行技術となる積層型チッ
プコイルを構成する各磁性体層を分解して示す斜視図で
ある。第２図は第１図の磁性体層を積層して得られた積
層型チップコイルを示す。 第３図はこの考案の一実施例を構成する各磁性体層を分
解して示す斜視図である。第４図は第３図の各磁性体層
を積層して得られた積層型チップコイルを示す。 図において、２１〜２８は磁性体層、２９〜３５は導電
パターン、３６〜４１はスルーホールである。FIG. 1 is an exploded perspective view showing each magnetic layer constituting a laminated chip coil, which is an interesting prior art of this invention. FIG. 2 shows a laminated chip coil obtained by laminating the magnetic layers shown in FIG. 1. FIG. 3 is an exploded perspective view showing each magnetic layer constituting an embodiment of this invention. FIG. 4 shows a laminated chip coil obtained by laminating the magnetic layers shown in FIG. 3. In the figure, 21 to 28 are magnetic layers, 29 to 35 are conductive patterns, and 36 to 41 are through holes.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 積層される複数層の磁性体層の各一方面上にインダクタ
ンス形成のための導電パターンが形成され、各導電パタ
ーンの端部が各磁性体層にそれぞれ設けられたスルーホ
ールを介して電気的に接続されて複数個の導電パターン
がコイル状に延びる状態とされる積層型チップコイルに
おいて、前記各スルーホールの磁性体層上での位置が、
この積層型チッチコイル全体として、分散されているこ
とを特徴とする、積層型チップコイル。A conductive pattern for forming inductance is formed on one side of each of the multiple magnetic layers stacked, and the ends of each conductive pattern are electrically connected through through holes provided in each magnetic layer. In a stacked chip coil in which a plurality of conductive patterns are connected and extend in a coil shape, the position of each through hole on the magnetic layer is
This multilayer chip coil is characterized in that the multilayer chip coil is dispersed throughout the entire multilayer chip coil.
JP3787783U 1983-03-16 1983-03-16 Laminated chip coil Pending JPS59145009U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3787783U JPS59145009U (en) 1983-03-16 1983-03-16 Laminated chip coil

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3787783U JPS59145009U (en) 1983-03-16 1983-03-16 Laminated chip coil

Publications (1)

Publication Number Publication Date
JPS59145009U true JPS59145009U (en) 1984-09-28

Family

ID=30168565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3787783U Pending JPS59145009U (en) 1983-03-16 1983-03-16 Laminated chip coil

Country Status (1)

Country Link
JP (1) JPS59145009U (en)

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