JPS6112210U

JPS6112210U - chip type inductor

Info

Publication number: JPS6112210U
Application number: JP9576384U
Authority: JP
Inventors: 利夫河端; 国三郎伴野
Original assignee: 株式会社村田製作所
Priority date: 1984-06-25
Filing date: 1984-06-25
Publication date: 1986-01-24

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を構成する磁性体、層１
〜１２を分解して示す斜視図である。第２図は第１図の磁性体層１〜１２を積層して得られる
積層体１３の斜視図である。第３図は第２図の線■一■に沿う断面図である。第４図は第２図の線ＩＶ−ＩＶに沿う断面図である。第５図は第２図の線■−■に沿う断面図である。第６図は第２図の線ＶＩ−ＶＩに沿う断面図である。第７図は第２図の積層体１３に外部電極２７．２８を形
成して得られたチツプ型インダクタを示す斜視図である
。第８図は第７図に示したチップ型インダクタにおける導
電経路等の接続態様を図解的に示す。図において、２，４，６，８．１０は第２種
磁性体層、３，５，７，９，１１，１２
は第１種磁性体層、１３は積層体、１４．１７〜２０は
接続用導電パターン、１５．２１〜２５は導電経路であ
る。Figure 1 shows a layer 1 of a magnetic material constituting an embodiment of this invention.
12 is an exploded perspective view. FIG. 2 is a perspective view of a laminate 13 obtained by laminating the magnetic layers 1 to 12 of FIG. 1. FIG. 3 is a sectional view taken along line 1-1 in FIG. 2. FIG. 4 is a sectional view taken along line IV--IV in FIG. 2. FIG. 5 is a sectional view taken along the line ■--■ in FIG. FIG. 6 is a sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a perspective view showing a chip type inductor obtained by forming external electrodes 27 and 28 on the laminate 13 of FIG. 2. FIG. FIG. 8 schematically shows a connection mode of conductive paths and the like in the chip type inductor shown in FIG. 7. In the figure, 2, 4, 6, 8. 10 is a second type magnetic layer, 3, 5, 7, 9, 11, 12
13 is a laminate, 14.17 to 20 are connection conductive patterns, and 15.21 to 25 are conductive paths.

Claims

[Scope of utility model registration request]

(1) A chip-type inductor that includes at least a part of a laminate of a plurality of magnetic layers, and a series of conductive paths extending in a coil shape within the interface of each of these magnetic layers to create an inductance component, wherein the magnetic layer is classified into two types: a first type magnetic layer with a linear conductive path formed on its upper surface, and a second type magnetic layer with a connecting conductive pattern formed on its lower surface. When you take out and look at two arbitrary layers of the first type magnetic material layer and one layer of the second kind magnetic material layer thereon, the conductive paths formed in each of the two layers of the first kind magnetic material layer. is the second
A chip-type inductor characterized in that a conductive pattern for connection formed in a seed magnetic layer is in common contact with the pattern.

(2) The first type magnetic layer has a planar shape obtained by dividing the planar shape of the laminate into two, and the second type magnetic layer has a planar shape in which the first type magnetic layer is divided into two parts. The planar shape is obtained by dividing the planar shape of the laminate into two in the intersecting direction, and the first type magnetic layer and the second type magnetic layer are alternately arranged so that one side of each layer intersects with each other. The chip-type inductor according to claim 1, which is stacked in a rotated direction.

(3) The intersecting direction is a right angle direction, and the first
3. The chip-type inductor according to claim 2, wherein the seed magnetic layer and the second type magnetic layer are alternately stacked with one side of each layer orthogonal to each other.

(4) A utility model registration claim in which each of the conductive paths on the first type magnetic layer extends by half a turn, each end of which reaches near a common side located on the boundary line of the division. A chip-type inductor according to the second or third range.