JPS58159717U - Laminated chip coil - Google Patents
Laminated chip coilInfo
- Publication number
- JPS58159717U JPS58159717U JP5696382U JP5696382U JPS58159717U JP S58159717 U JPS58159717 U JP S58159717U JP 5696382 U JP5696382 U JP 5696382U JP 5696382 U JP5696382 U JP 5696382U JP S58159717 U JPS58159717 U JP S58159717U
- Authority
- JP
- Japan
- Prior art keywords
- chip coil
- conductive
- laminated chip
- conductive patterns
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ａ、 ｂはこの考案の一実施例に使用するチッ
プコイルの平面図とそのｘ−Ｘ線による断面図、第２図
は導電パターンの接続を示す積層説明図、第３図ａ、
ｂはこの考案の他の実施例に使用するチップコイルの
平面図とそのＹ−Ｙ線による断面図、第４図ａ、 ｂ
はこの考案のさらに他の実施例に使用するチップコイル
の平面図とそのＺ−Ｚ線による断面図である。
図中、１はチップコイル、２は絶縁シート、３Ａ、３Ｂ
は導電パターン、４は中心、５Ａ、 ５Ｂは電極、６
Ａ、５Ｂはスペーサ、７は絶縁層である。
■
Ｌ７
３Ａ２６Ａ
３ｓFigures 1a and 1b are a plan view of a chip coil used in an embodiment of this invention and its cross-sectional view taken along the line
b is a plan view of a chip coil used in another embodiment of this invention and its cross-sectional view taken along the Y-Y line; FIGS. 4a and b
2 is a plan view of a chip coil used in yet another embodiment of this invention and a cross-sectional view thereof taken along the Z-Z line. In the figure, 1 is a chip coil, 2 is an insulating sheet, 3A, 3B
is a conductive pattern, 4 is the center, 5A, 5B are electrodes, 6
A and 5B are spacers, and 7 is an insulating layer. ■ L7 3A26A 3s
Claims (1)
ともに所定位置で前記両導電パターンを導通させ、前記
絶縁シートに前記導電パターンと導通している電極と、
所要数のスペーサを設けたチップコイルを構成し、前記
チップコイルを順次積層したときに各層の前記導電パタ
ーンを前記電極で導通させるとともに前記スペーサで前
記導電パターンの間隔を保持したことを特徴とする積層
チップコイル。A conductive pattern of a predetermined shape is provided on both sides of an insulating sheet, and both conductive patterns are electrically connected at a predetermined position, and an electrode is electrically connected to the conductive pattern on the insulating sheet;
A chip coil is configured with a required number of spacers, and when the chip coils are sequentially stacked, the conductive patterns in each layer are made conductive by the electrodes, and the spacers maintain the spacing between the conductive patterns. Laminated chip coil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5696382U JPS58159717U (en) | 1982-04-21 | 1982-04-21 | Laminated chip coil |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5696382U JPS58159717U (en) | 1982-04-21 | 1982-04-21 | Laminated chip coil |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58159717U true JPS58159717U (en) | 1983-10-25 |
Family
ID=30067453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5696382U Pending JPS58159717U (en) | 1982-04-21 | 1982-04-21 | Laminated chip coil |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159717U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6261305A (en) * | 1985-09-11 | 1987-03-18 | Murata Mfg Co Ltd | Laminated chip coil |
-
1982
- 1982-04-21 JP JP5696382U patent/JPS58159717U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6261305A (en) * | 1985-09-11 | 1987-03-18 | Murata Mfg Co Ltd | Laminated chip coil |
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