JPS6173357A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6173357A
JPS6173357A JP19465384A JP19465384A JPS6173357A JP S6173357 A JPS6173357 A JP S6173357A JP 19465384 A JP19465384 A JP 19465384A JP 19465384 A JP19465384 A JP 19465384A JP S6173357 A JPS6173357 A JP S6173357A
Authority
JP
Japan
Prior art keywords
fuse
wiring
section
semiconductor element
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19465384A
Other languages
Japanese (ja)
Inventor
Itaru Muramatsu
村松 至
Hajime Terakado
寺門 肇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19465384A priority Critical patent/JPS6173357A/en
Publication of JPS6173357A publication Critical patent/JPS6173357A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

PURPOSE:To protect a peripheral electronic part positively by incorporating a fuse element into one part of a conductive path in semiconductor element itself. CONSTITUTION:A bump electrode 3 is formed onto the upper surface of a substrate 1 in a projecting manner under the state in which it is connected to an N region. A wiring 4 as a conductive path connecting an N region and a P region on the outside is shaped onto an insulating layer 2 in the upper surface section of the substrate 1. A fuse section 5 functioning as a fuse element is formed to the intermediate section of the wiring 4 under a fusion-cutting-able state by overcurrents higher than a fixed value. The wiring 4 and the fuse section 5 can be shaped easily by utilizing a semiconductor element manufacturing process. When overcurrents higher than the fixed value flow through the wiring 4, the fuse section 5 is fusion-cut at a time earlier than other sections, and the fuse section 5 can ensure protections to other peripheral electronic parts and peripheral electronic apparatus.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体技術、特に半導体素子およびその周辺機
器を過電流から保護するのに適用して効果のある技術に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor technology, and particularly to technology that is effective when applied to protect semiconductor devices and their peripheral equipment from overcurrent.

〔背景技術〕[Background technology]

半導体素子およびそれを用いた各種周辺機器において過
電流が流れることにより半導体素子や周辺機器が破壊さ
れることを防止するため、何らかの保護対策を講じるこ
とが考えられる。
It is conceivable to take some kind of protective measures to prevent semiconductor elements and various peripheral devices using the same from being destroyed by overcurrent flowing therein.

そこで、7エーズ専用の電子部品を用いることが考えら
れる。たとえば、特開昭55−100630号公報には
、7エーズエレメントを低抵抗基板上に形成したフェー
ズが提案されている。
Therefore, it is conceivable to use electronic components exclusively for 7A. For example, Japanese Unexamined Patent Publication No. 100630/1983 proposes a phase in which a 7A element is formed on a low resistance substrate.

ところが、この種のフェーズはそれ自体がフユーズ目的
のために専用されるものであり、そのフェーズを別個に
取り付けなければならな(・ため、構造が大型化し、ま
た作業が面倒になる等の問題がある。
However, this type of phase is itself dedicated for fuse purposes, and must be installed separately (this results in problems such as an enlarged structure and troublesome work). There is.

また、半導体素子では過電流による故障モードはショー
ト状態とオープン状態との2つの状態になる。この過電
流によるショート、トプンの2つの状態が予期できず、
過電流により必ずオープン状態になることが保証できな
いため、周辺電子部品に対する保護が不確実になるとい
う問題があることを本発明者は見い出した。
Furthermore, in a semiconductor device, there are two failure modes due to overcurrent: a short-circuit state and an open state. Two conditions, short circuit and topun due to this overcurrent, cannot be predicted.
The inventor has discovered that there is a problem in that protection for peripheral electronic components is uncertain because it cannot be guaranteed that an open state will occur due to overcurrent.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、過電流により確実にオープン状態とな
り、周辺電子部品を確実に保護できる半導体技術を提供
することにある、 本発明の他の目的は、半導体素子製造プロセスにより容
易に製造できるフェーズ素子を有する半導体技術を提供
することにある。
Another object of the present invention is to provide a semiconductor technology that can reliably enter an open state due to overcurrent and protect peripheral electronic components. The purpose of the present invention is to provide a semiconductor technology having an element.

本発明の前記ならびにその他の目的と新規な特徴は、本
明a書の記述および添付図面から明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体素子自体の導電経路の一部にフーーズ
素子を組み込むことにより、過電流の発生時にはこのフ
ーーズ素子を確実にオープン状態とし、周辺電子部品の
確実な保護を可能にするものである。
That is, by incorporating a Who's element into a part of the conductive path of the semiconductor element itself, the Who's element is reliably brought into an open state when an overcurrent occurs, thereby making it possible to reliably protect peripheral electronic components.

〔実施例]〕〔Example]〕

第1図(a)と(b)はそれぞれ本発明の一実施例であ
る半導体素子の平面図と断面図である。
FIGS. 1(a) and 1(b) are a plan view and a sectional view, respectively, of a semiconductor device according to an embodiment of the present invention.

この実施例における半導体素子はいわゆるダブルヒート
シンク型ダイオード(DHD型ダイオード)σ)構造よ
りなるものである。
The semiconductor element in this embodiment has a so-called double heat sink diode (DHD diode) structure.

すなわち、このDHD型ダイオード用の半導体素子Sは
、シリコン(Si)等の基板1を有し、この基板1はN
、P、Hの各領域が形成されている。
That is, this semiconductor element S for a DHD type diode has a substrate 1 made of silicon (Si) or the like, and this substrate 1 is made of N
, P, and H regions are formed.

前記基板1の上には、たとえばSin、よりなる絶縁層
2がたとえばCVD法を用いて半導体製造プロセス技術
で形成されている。
On the substrate 1, an insulating layer 2 made of, for example, Sin is formed by semiconductor manufacturing process technology using, for example, the CVD method.

また、基板1のほぼ中央部上面には、たとえば銀(AJ
’)材料よりなるバンプ電極3が中央N領域と接続され
た状態で突設されている。
Further, on the upper surface of the substantially central portion of the substrate 1, for example, silver (AJ
') A bump electrode 3 made of a material is protruded and connected to the central N region.

さらに、基板1の上面部には、外側のN領域とP領域と
を接続する導電路としての配線4がたとえばアルミニウ
ム(、す)の蒸着によりP2縁層2上に形成されている
Further, on the upper surface of the substrate 1, a wiring 4 as a conductive path connecting the outer N region and the P region is formed on the P2 edge layer 2 by vapor deposition of aluminum, for example.

この配線4の途中の部分には、フェーズ素子としての働
きをするフーーズ部5が所定値以上の過電流により溶断
可能に形成されている。
A whoosh portion 5 that functions as a phase element is formed in the middle of this wiring 4 so that it can be blown out by an overcurrent of a predetermined value or more.

前記配線4およびフーーズ部5は半導体素子製造プロセ
スを利用することによりいずれもへβ蒸着等で容易に形
成することができるものである。
The wiring 4 and the foosing portion 5 can both be easily formed by β evaporation or the like by utilizing a semiconductor element manufacturing process.

すなわち、本実施例のフユーズ部5は配線4と同時に形
成されているが、他の部分よりも第1図(a)の如く細
い線巾で形成されている。
That is, although the fuse portion 5 of this embodiment is formed at the same time as the wiring 4, it is formed with a narrower line width than other portions as shown in FIG. 1(a).

したがって、配線4に所定値以上の過電流が流れた場合
、フユーズ部5は他の部分よりも電流容量が小さ−・の
で、他の部分よりも該フユーズ部5が早く溶断されるこ
とになり、該フユーズ部5は他の周辺電子部品や周辺電
子機器に対する保護を確実に図ることのできるフェーズ
素子を果たすことが可能である。
Therefore, when an overcurrent of more than a predetermined value flows through the wiring 4, the fuse section 5 has a smaller current capacity than other sections, so the fuse section 5 will be blown out earlier than the other sections. The fuse section 5 can function as a phase element that can reliably protect other peripheral electronic components and equipment.

なお、第1図(a) 、 (b)に示す半導体素子を用
いて半導体装置の一例としてのDHD型ダイオードを構
成した実施例は第5図に示されている。この実施例にお
いて、半導体素子Sはガラス管6内で2つのり一ドレス
型の面装着用電極7.7間に挾持された状、態で封止さ
れている。
Incidentally, an embodiment in which a DHD type diode as an example of a semiconductor device is constructed using the semiconductor elements shown in FIGS. 1(a) and 1(b) is shown in FIG. In this embodiment, the semiconductor element S is sandwiched and sealed in the glass tube 6 between two glue-less type surface mounting electrodes 7.7.

し実施例2〕 第2図(a)と(b)はそれぞれ本発明の他の実施例に
おける半導体素子の平面図と断面図である。
Embodiment 2] FIGS. 2(a) and 2(b) are a plan view and a sectional view, respectively, of a semiconductor element in another embodiment of the present invention.

本実施例の半導体素子Sはたとえばレジンモールド型σ
)ダイオードに使用されるものであり、その基板1の中
央上部にP領域と接続された配線4の一部には、他の部
分よりも細巾ハフユーズ部5がAa蒸着等の半導体素子
製造プロセス技術を用いて形成されている。
The semiconductor element S of this embodiment is, for example, a resin mold type σ
) used in a diode, and a part of the wiring 4 connected to the P region at the upper center of the substrate 1 has a thinner used part 5 than the other part, which is formed by a semiconductor element manufacturing process such as Aa vapor deposition. It is formed using technology.

したがって、本実施例においても、配線4に過電流が流
れた場合、フーーズ部5は他の部分よりも電流容量が小
さいので、該フユーズ部5が他の部分よりも早く溶断さ
れ、フーーズとしての機能を果たすことができる。
Therefore, in this embodiment as well, when an overcurrent flows through the wiring 4, since the fuse portion 5 has a smaller current capacity than other portions, the fuse portion 5 is blown out earlier than the other portions, and the fuse portion 5 is blown out earlier than the other portions. able to perform a function.

〔実施例3〕 第3図(a)とΦ)はそれぞれ本発明のさらに他の実施
例における半導体素子の平面図と断面図である。
[Embodiment 3] FIGS. 3(a) and Φ) are a plan view and a sectional view, respectively, of a semiconductor element in still another embodiment of the present invention.

本実施例の半導体素子Sはたとえばバイポーラ型のトラ
ンジスタの如き半導体装置に用(・られるものである。
The semiconductor element S of this embodiment is used in a semiconductor device such as a bipolar transistor.

この半導体素子Sにおいても、基板]上に配線4が形成
され、この配線4の途中には、他の部分よりも細巾のフ
ーーズ部5が設けられ、フユーズ機能を果たすようにな
っている。
In this semiconductor element S as well, a wiring 4 is formed on the substrate, and a whoosh portion 5, which is narrower than other parts, is provided in the middle of the wiring 4 to function as a fuse.

〔実施例4〕 第4図は本発明の他の実施例である半導体素子の部分断
面図である。
[Embodiment 4] FIG. 4 is a partial cross-sectional view of a semiconductor device according to another embodiment of the present invention.

本実施例の半導体素子SはたとえばTTL回路用のもの
であり、基板1のN領域にN1領域として形成された4
電領域8に接続された配線4の一部に細巾のフユーズ部
5が形成されている。
The semiconductor element S of this embodiment is for, for example, a TTL circuit, and the semiconductor element S is for a TTL circuit, and a
A narrow fuse portion 5 is formed in a part of the wiring 4 connected to the power region 8.

このフーーズ部5も過電流で溶断されてフユーズ機能を
果たすものである。
This fuse portion 5 also functions as a fuse by being blown by overcurrent.

〔効果〕〔effect〕

(1)  半導体素子自体の導電経路の一部にフーーズ
素子を組み込むことにより、過電流の発生時にはこのフ
ーーズ素子が溶断されるので、周辺電子部品や電子機器
等を確実に保護することができる。
(1) By incorporating a Who's element into a part of the conductive path of the semiconductor element itself, the Who's element is blown out when an overcurrent occurs, so peripheral electronic components, electronic equipment, etc. can be reliably protected.

(2)  フーーズ素子を半導体素子製造プロセスによ
り形成することによって、フユーズ素子の形成を容易に
行うことができる。
(2) By forming the fuse element using a semiconductor element manufacturing process, the fuse element can be easily formed.

(3)前記(1) 、 (21により、低コストでフユ
ーズ機能を備えた半導体素子を提供できる。
(3) According to (1) and (21) above, a semiconductor element having a fuse function can be provided at low cost.

(4)  前記(1) 、 (21により、フェーズ専
用の素子やその接続等を不要とすることができる。
(4) According to (1) and (21) above, it is possible to eliminate the need for phase-dedicated elements and their connections.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることは〜・うまでもない。
Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and various changes can be made without departing from the gist of the invention. It's no good.

たとえば、フーーズ素子を配線部とは異なる材料や厚さ
のもので作ること等も可能である。
For example, it is possible to make the Who's element with a material and thickness different from that of the wiring portion.

C利用分野〕 以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるDHD型ダイオード
等に適用した場合について説明したが、それに限定され
るものではなく、たとえば、バイポーラまたはMOS型
のIC等に広く適用できる。
C Field of Application] The above explanation has mainly focused on the case where the invention made by the present inventor is applied to the field of application which is the background of the invention, such as DHD type diodes, but is not limited thereto; for example, bipolar Alternatively, it can be widely applied to MOS type ICs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)と(b)はそれぞれ本発明の一実施例にお
ける半導体素子の平面図と断面図、 第2図(a)と(b)はそれぞれ本発明の他の実施例に
おける半導体素子の平面図と断面図、 第3図(a)と(b)はそれぞれ本発明のさらに他の実
施例における半導体素子の平面図と断面図、第4図は本
発明のさらに他の実施例における断面図、 第5図は第1図の半導体素子を用いて構成された本発明
の半導体装置の一実施例であるDHD型ダイオードを示
す断面図である。 1・・・基板、2・・・絶縁層、3・・・バンプ電極、
4・・・配線(導電経路)、5・・・フユーズ部(フユ
ーズ素子)、6・・・ガラス管、7・・・電極、8・・
・導電領域。 第   1  図 (即
FIGS. 1(a) and (b) are respectively a plan view and a sectional view of a semiconductor device according to one embodiment of the present invention, and FIGS. 2(a) and (b) are respectively a semiconductor device according to another embodiment of the present invention. FIGS. 3(a) and 3(b) are a plan view and a sectional view of a semiconductor element according to still another embodiment of the present invention, and FIG. 4 is a diagram showing a semiconductor device according to still another embodiment of the present invention. Cross-sectional view FIG. 5 is a cross-sectional view showing a DHD type diode which is an embodiment of the semiconductor device of the present invention constructed using the semiconductor element shown in FIG. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Insulating layer, 3... Bump electrode,
4... Wiring (conductive path), 5... Fuse part (fuse element), 6... Glass tube, 7... Electrode, 8...
・Conductive area. Figure 1 (immediately

Claims (1)

【特許請求の範囲】 1、半導体素子自体の導電経路の一部にフューズ素子を
組み込んでなることを特徴とする半導体装置。 2、フューズ素子が半導体素子製造プロセスにより形成
されることを特徴とする特許請求の範囲第1項記載の半
導体装置
[Scope of Claims] 1. A semiconductor device characterized by incorporating a fuse element into a part of the conductive path of the semiconductor element itself. 2. The semiconductor device according to claim 1, wherein the fuse element is formed by a semiconductor element manufacturing process.
JP19465384A 1984-09-19 1984-09-19 Semiconductor device Pending JPS6173357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19465384A JPS6173357A (en) 1984-09-19 1984-09-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19465384A JPS6173357A (en) 1984-09-19 1984-09-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6173357A true JPS6173357A (en) 1986-04-15

Family

ID=16328083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19465384A Pending JPS6173357A (en) 1984-09-19 1984-09-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6173357A (en)

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