JPH03104155A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03104155A JPH03104155A JP24151289A JP24151289A JPH03104155A JP H03104155 A JPH03104155 A JP H03104155A JP 24151289 A JP24151289 A JP 24151289A JP 24151289 A JP24151289 A JP 24151289A JP H03104155 A JPH03104155 A JP H03104155A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- bending part
- resistance layer
- resistor
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000005452 bending Methods 0.000 claims abstract 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 239000007772 electrode material Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
- 230000020169 heat generation Effects 0.000 abstract description 5
- 230000008020 evaporation Effects 0.000 abstract description 4
- 238000001704 evaporation Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000004927 fusion Effects 0.000 abstract 2
- 230000001681 protective effect Effects 0.000 description 21
- 239000010410 layer Substances 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 5
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、入力保護抵抗の保護動作に伴う溶断事故を防
止できる半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor device that can prevent a melting accident caused by a protective operation of an input protection resistor.
（口〉従来の技術
ＭＯＳ型ＬＳＩにおいては、ゲート保護のために入力保
護回路を設けている。この保護回路としては、例えば特
開昭６２−１２８５６５号公報に記載されているような
保護抵抗とダイ才一ドを組み合わせたものが代表的であ
る。(Example) In a conventional MOS type LSI, an input protection circuit is provided for gate protection.This protection circuit includes a protection resistor and a protection resistor as described in, for example, Japanese Patent Application Laid-Open No. 62-128565. A typical example is a combination of Dai and Saiichi.
第４図にその回路図を示す。同図において、（１〉は入
カパッド、（２）は入力トランジスタ、（３〉はダイ才
一ドを構成する為の素子、（４）は入力トランジスタ（
２）のゲートと入力パッド（１）との間に接続された入
力保護抵抗である。Figure 4 shows the circuit diagram. In the figure, (1> is an input pad, (2) is an input transistor, (3> is an element for configuring a die capacitor, and (4) is an input transistor (
2) is an input protection resistor connected between the gate of the input pad (1) and the input pad (1).
入力保護抵抗（４）には、ＭＯＳＬＳＩプロセスにおけ
る製造の容易さから、ゲートと同じポリシノコン（Ｐｏ
ｌｙ−５４）が主に用いられる。その構造は第５図と第
６図に示すように、チップ周囲のフィールド酸化膜（５
〉上にポリシリコンから成る保護抵抗（６）が形成され
、絶縁膜（７）に開けたコンタクトホール（８）を介し
てアルミニウム〈Ａｌ〉から或る電極配線（９〉が保護
抵抗（６）の一端にコンタクトし、電極配線（９〉の他
端はボンディングバッド（１）を構成し、保護抵抗（６
）の表面はいくつかの層間絶縁膜（７）（１０）とパッ
シベーション被膜（１１）とで覆われている。The input protection resistor (4) is made of the same polysinoconductor as the gate due to ease of manufacturing in the MOSLSI process.
ly-54) is mainly used. Its structure is shown in Figures 5 and 6, as shown in Figures 5 and 6.
> A protective resistor (6) made of polysilicon is formed on the protective resistor (6), and a certain electrode wiring (9) made of aluminum is connected to the protective resistor (6) through a contact hole (8) made in the insulating film (7). The other end of the electrode wiring (9) constitutes a bonding pad (1), and the protective resistor (6
) is covered with several interlayer insulating films (7), (10) and a passivation film (11).
（ハ）発明が解決しようとする課題
しかしながら、従来の保護回路が保護動作した場合、ジ
クザグに延在する保護抵抗ク６）の折り曲げ部（１２）
において電流が集中する為、その発熱によって保護抵抗
（６）が第５図図示Ａのように蒸発し、極端な場合には
、又は蒸発がたび重なった場合には溶断してしまう欠点
があった。(C) Problems to be Solved by the Invention However, when the conventional protection circuit performs a protection operation, the bent portion (12) of the protection resistor 6) extending in a zigzag pattern
Since the current is concentrated in the protective resistor (6), the heat generated causes the protective resistor (6) to evaporate as shown in Figure 5 A, and in extreme cases, or if the evaporation occurs repeatedly, it may melt. .
（二〉課題を解決するための手段
本発明は上記従来の欠点に鑑み成されたもので、保護抵
抗〈２２〉の折り曲げ部（３２）上に、保護抵抗（２２
〉材料より比抵抗が小さい材料から成る導電部材（２３
）を絶縁膜（２６）のコンタクトホール（２４）を介し
てコンタクトさせることにより、従来の欠点を解消した
半導体装置を提供するものである。(2) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks of the conventional art.
〉Conductive member (23
) is contacted through a contact hole (24) of an insulating film (26), thereby providing a semiconductor device that eliminates the conventional drawbacks.
（ホ〉作用
本発明によれば、導電部材（２３）がコンタクトするこ
とにより、保護抵抗（２２）の折り曲げ部（３２）の抵
抗成分が実質的に零になるので、抵抗分に起するボリシ
リコン層の発熱を防止できる．（へ）実施例
以下に本発明の一実施例を図面を参照しながら詳細に説
明する。(E) Effect According to the present invention, the resistance component of the bent portion (32) of the protective resistor (22) becomes substantially zero by contacting the conductive member (23), so that the voltage caused by the resistance component is reduced. Heat generation in the silicon layer can be prevented.(f) Example An example of the present invention will be described below in detail with reference to the drawings.
第１図は本実施例の構成を示す平面図、第２図は断面図
である。（２１）は入カパッド、（２２）は入力パッド
（２１）とＭＯＳ｝−ランジスタのゲートとの間に接続
される入力保護抵抗、（２３）はコンタクト孔（２４）
を介して保護抵抗（２２）の表面に接触する導電部材で
ある。FIG. 1 is a plan view showing the configuration of this embodiment, and FIG. 2 is a sectional view. (21) is the input pad, (22) is the input protection resistor connected between the input pad (21) and the gate of the MOS}-transistor, (23) is the contact hole (24)
This is a conductive member that comes into contact with the surface of the protective resistor (22) via the protective resistor (22).
保護抵抗（２２）は第２図に示す如く、チップ周辺部の
フィールド酸化膜（２５〉上にゲート電極形成と同時的
な膜厚１０００〜２０００人のポリシリコン（ｐｏｌｙ
−Ｓｉ）層の堆積とバターニングによって形成され、ゲ
ート電極とは異る濃度の不純物がドーブされて所望のシ
ート抵抗値に形成される。As shown in Figure 2, the protective resistor (22) is made of polysilicon (polysilicon) with a film thickness of 1000 to 2000 at the same time as gate electrode formation on the field oxide film (25) in the peripheral area of the chip.
-Si) layer is formed by deposition and patterning, and is doped with impurities at a concentration different from that of the gate electrode to form a desired sheet resistance value.
保護抵抗（２２）の一端は、層間絶縁膜（２６〉に開け
られたコンタクトホール（２７）を介して２層目配線と
なるＡＮ電極（２８）とコンタクトし、２層目ｋｌ電極
ク２８）は層間絶縁膜ク２６）上を延在して３層目配線
となるＡ２電極（２９）と共に入カパッド（２１）を構
成する。保護抵抗（２２）の他端は、入力ＭＯＳトラン
ジスタのゲートにポリシリコン層が連続して、又は２層
目Ａｆｆｉｔ極（２８）を介して接続される。One end of the protective resistor (22) contacts the AN electrode (28) which becomes the second layer wiring through the contact hole (27) made in the interlayer insulating film (26), and connects to the second layer kl electrode (28). forms an input pad (21) together with the A2 electrode (29) which extends over the interlayer insulating film (26) and becomes the third layer wiring. The other end of the protection resistor (22) is connected to the gate of the input MOS transistor through a continuous polysilicon layer or via a second layer Affit pole (28).
２層目Ａ２電極（２８）と３層目八〇電極（２９）とは
コンタクト部分を除き層間絶縁膜（３０〉で層間絶縁さ
れ、３層目Ａｆｆｉ電極（２９）の表面は入カパッド（
２１）部分を除きパッシベーション被膜（３１）で覆わ
れる．層間絶縁膜（２６）（３０）は膜厚１．０〜２．
０μのＰＳＧ，ＢＰＳＧ，ＳＯＧ等、パッシベーション
被膜＜３１）は膜厚２．０ 〜４．ｏμのｐｓＧ， ポ
ｌＪイミド系樹脂等、電極（２８）（２９）はＡｌの他
Ａ之−Ｓｉ等の合金もある。The second layer A2 electrode (28) and the third layer 80 electrode (29) are insulated with an interlayer insulating film (30) except for the contact part, and the surface of the third layer Affi electrode (29) is covered with an input pad (
21) is covered with a passivation film (31). The interlayer insulating films (26) and (30) have a film thickness of 1.0 to 2.
Passivation films such as 0μ PSG, BPSG, SOG, etc. <31) have a film thickness of 2.0 to 4. The electrodes (28) and (29) are made of alloys such as oμ psG, polJ imide resin, etc., as well as Al and A to -Si.
導電部材（２３〉は、２層目ＡＩ２電極（２８〉の製造
プロセスと同時に堆積・パターニングして形成される。The conductive member (23>) is formed by deposition and patterning simultaneously with the manufacturing process of the second layer AI2 electrode (28>).
ジクザグ状に折れ曲り延在する保護抵抗（２２）の折り
曲げ部（３２）上に設置され、溶断の危険性から判断し
てパッド（２１）との接続部分から数えて１番目の導電
部材（２３〉は必要不可決、２番目（２３ｂ）、３番目
（２３ｃ）以降は必然性に応じて設ける。The conductive member (23) is installed on the bent part (32) of the protective resistor (22) that extends in a zigzag shape, and is the first conductive member (23) counted from the connection part with the pad (21), judging from the risk of melting. > is not necessary, and the second (23b), third (23c) and subsequent ones are provided according to necessity.
導電部材（２３〉と保護抵抗（２２）とのコンタクトホ
ール〈２４〉は、通常の正方形の他、第３図に示す如く
、５角形以上の多角型又は円形として出来るだけ角部を
無くした方が電流集中の危惧が少い。The contact hole <24> between the conductive member (23>) and the protective resistor (22) can be made of a regular square shape, a polygonal shape with more than 5 sides, or a circular shape with as few corners as possible, as shown in Figure 3. However, there is little risk of current concentration.
また、保護抵抗（２２〉の谷側折り曲げ部（３３）も同
様の理由で斜めにした方が良い。Furthermore, it is better to make the valley-side bent portion (33) of the protective resistor (22) oblique for the same reason.
上記本願発明によれば、保護抵抗（２２）の折り曲げ部
（３２〉上に比抵抗が小さい導電部材（２３）がコンタ
クトするので、折り曲げ部（３２）の抵抗或分を実質的
に零に等しくできる。その為静電パルスによる電流ｉは
コンタクトホール（２４）内をスムーズに流れるので、
この部分での局部的な発熱を抑えられ、よって折り曲げ
部（３２）のポリシリコンの蒸発を抑えることができる
。According to the invention of the present application, the conductive member (23) having a low specific resistance is in contact with the bent portion (32) of the protective resistor (22), so that the resistance of the bent portion (32) is made substantially equal to zero. Therefore, the current i caused by the electrostatic pulse flows smoothly inside the contact hole (24), so
Local heat generation at this portion can be suppressed, and therefore evaporation of polysilicon at the bent portion (32) can be suppressed.
導電部材（２３）はまた、例えばアルミニウムを選択す
れば、ポリシリコンの熱伝導度１ ６ ８Ｗｍ−’ｋ−
’に比べてアルミニウムの熱伝導度は２ ３ ６Ｗｍ−
’ｋ−１と高いので、保護抵抗（２２）の発熱を吸収す
ることができる。そして導電部材ク２３）によって放熱
面積が増大すること、及びポリシリコン層より放熱面が
パッシベーション膜（３１〉表面に接近することから、
放熱効率を改善でき、保護抵抗（２２）の溶断事故をさ
らに防止することができる。The conductive member (23) may also have a thermal conductivity of polysilicon of 1 6 8 Wm-'k-, if aluminum is selected, for example.
' The thermal conductivity of aluminum is 2 3 6 Wm-
Since it is as high as 'k-1, it is possible to absorb the heat generated by the protective resistor (22). Since the heat dissipation area is increased by the conductive member 23) and the heat dissipation surface is closer to the passivation film (31> surface than the polysilicon layer),
Heat dissipation efficiency can be improved, and melting accidents of the protective resistor (22) can be further prevented.
（ト）発明の効果
以上に説明した通り、本発明によれば導電部材（２３〉
によって折り曲げ部ク３２〉の電流集中による局部的な
発熱を防止し、ポリシリコン層の蒸発を防止して保護抵
抗（２２〉の溶断事故を未然に防止できる利点を有する
。(g) Effects of the invention As explained above, according to the present invention, the conductive member (23)
This has the advantage of preventing local heat generation due to current concentration in the bent portion 32>, preventing evaporation of the polysilicon layer, and preventing a melting accident of the protective resistor (22>).
また、導電部材（２３）と保護抵抗（２２）とを熱的に
もコンタクトさせることにより、保護抵抗（２２）の発
熱を効果的に放熱して前記利点を一層増大できる。Further, by bringing the conductive member (23) and the protective resistor (22) into thermal contact, the heat generated by the protective resistor (22) can be effectively dissipated, thereby further increasing the above-mentioned advantages.
さらに、導電部材ク２３〉は多層配線構造を利用して形
或できるので、工程数の増大が無い利点をも有する。Furthermore, since the conductive member 23> can be formed using a multilayer wiring structure, it also has the advantage that the number of steps does not increase.
第１図、第２図および第３図は各々本発明を説明する為
の平面図、断面図および拡大平面図、第４図、第５図お
よび第６図は各々従来例を説明する為の回路図、平面図
および断面図である。1, 2, and 3 are a plan view, a sectional view, and an enlarged plan view for explaining the present invention, and FIGS. 4, 5, and 6 are for explaining a conventional example, respectively. They are a circuit diagram, a plan view, and a sectional view.
Claims (5)
、このＭＩＳＦＥＴのゲート保護のためにそのゲートと
入力パッドとの間に電気的接続され、少なくとも１箇所
を折り曲げて延在する半導体抵抗層と、前記半導体抵抗
層の表面を覆う絶縁膜とを有する半導体装置において、 前記半導体抵抗層の折り曲げ部上に、前記絶縁膜のコン
タクトホールを介してこれと接触し、前記半導体抵抗層
より比抵抗が小さい導電部材を設け、前記半導体抵抗層
の折り曲げ部の抵抗分を実質的に除去したことを特徴と
する半導体装置。(1) A MISFET formed on one main surface of a semiconductor substrate, and a semiconductor resistance layer that is electrically connected between the gate and the input pad to protect the gate of the MISFET, and that extends by bending at least one place. and an insulating film covering a surface of the semiconductor resistance layer, the semiconductor resistance layer being in contact with the bent portion of the semiconductor resistance layer through a contact hole in the insulating film, and having a specific resistance lower than the semiconductor resistance layer. 1. A semiconductor device characterized in that a conductive member having a small resistance is provided to substantially eliminate a resistance component of a bent portion of the semiconductor resistance layer.
特徴とする請求項第１項に記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the semiconductor resistance layer is made of polysilicon.
を特徴とする請求項第１項に記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the conductive member is made of an electrode material for multilayer wiring.
主体とする合金から成ることを特徴とする請求項第３項
に記載の半導体装置。(4) The semiconductor device according to claim 3, wherein the electrode material is made of aluminum or an alloy mainly composed of aluminum.
触していることを特徴とする請求項第１項に記載の半導
体装置。(5) The semiconductor device according to claim 1, wherein the semiconductor resistance layer and the conductive member are also in thermal contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24151289A JPH03104155A (en) | 1989-09-18 | 1989-09-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24151289A JPH03104155A (en) | 1989-09-18 | 1989-09-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104155A true JPH03104155A (en) | 1991-05-01 |
Family
ID=17075442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24151289A Pending JPH03104155A (en) | 1989-09-18 | 1989-09-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104155A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007250757A (en) * | 2006-03-15 | 2007-09-27 | Sanyo Electric Co Ltd | Semiconductor device, and its automatic placement and wiring method |
-
1989
- 1989-09-18 JP JP24151289A patent/JPH03104155A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007250757A (en) * | 2006-03-15 | 2007-09-27 | Sanyo Electric Co Ltd | Semiconductor device, and its automatic placement and wiring method |
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