JPH08203952A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08203952A
JPH08203952A JP997395A JP997395A JPH08203952A JP H08203952 A JPH08203952 A JP H08203952A JP 997395 A JP997395 A JP 997395A JP 997395 A JP997395 A JP 997395A JP H08203952 A JPH08203952 A JP H08203952A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
conductive layer
contact
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP997395A
Other languages
Japanese (ja)
Inventor
Kuniyuki Hishinuma
邦之 菱沼
Noboru Motai
昇 罍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Precision Circuits Inc
Original Assignee
Nippon Precision Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Precision Circuits Inc filed Critical Nippon Precision Circuits Inc
Priority to JP997395A priority Critical patent/JPH08203952A/en
Publication of JPH08203952A publication Critical patent/JPH08203952A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05085Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089Disposition of the additional element
    • H01L2224/05093Disposition of the additional element of a plurality of vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05085Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089Disposition of the additional element
    • H01L2224/05093Disposition of the additional element of a plurality of vias
    • H01L2224/05096Uniform arrangement, i.e. array

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To prevent film exfoliation in a bonding pad part. CONSTITUTION: A semiconductor device is provided with a first insulating layer 12 formed on the main surface side of a semiconductor substrate 11, a first conducting layer 13 which is in contact with the first insulating layer 12, a second insulating layer 14 which is formed on the first insulating layer 13 and has an aperture part 14a, a second conducting layer 15 which is in contact with the first conducting layer 13 in the aperture part 14a, and a third conducting layer 16 which is in contact with the second conducting layer 15 and turns to the connection terminal of a bonding wire.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本願は、半導体装置、特にそのボ
ンディングパッド部の構成に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present application relates to a semiconductor device, and more particularly to a structure of a bonding pad portion thereof.

【0002】[0002]

【従来の技術】図4は、従来例を示したものであり、半
導体装置のボンディングパッド部の構成を示したもので
ある。21はシリコン基板、22は層間絶縁層、23は
バリアメタル層、24はボンディングパッドとなるアル
ミニウム層、25は保護絶縁層、25aは保護絶縁層に
設けられた開口部である。バリアメタル層23およびア
ルミニウム層24は、MOSトランジスタのソ―ス・ド
レイン用コンタクトのバリアメタル層/アルミニウム層
のパタ―ニングと同時にパタ―ニングされる。したがっ
て、層間絶縁層22とアルミニウム層24との間に必然
的にバリアメタル層23が形成されることになる。
2. Description of the Related Art FIG. 4 shows a conventional example and shows a structure of a bonding pad portion of a semiconductor device. Reference numeral 21 is a silicon substrate, 22 is an interlayer insulating layer, 23 is a barrier metal layer, 24 is an aluminum layer serving as a bonding pad, 25 is a protective insulating layer, and 25a is an opening provided in the protective insulating layer. The barrier metal layer 23 and the aluminum layer 24 are patterned simultaneously with the patterning of the barrier metal layer / aluminum layer of the source / drain contact of the MOS transistor. Therefore, the barrier metal layer 23 is inevitably formed between the interlayer insulating layer 22 and the aluminum layer 24.

【0003】[0003]

【発明が解決しようとする課題】しかし、一般的に層間
絶縁層22(酸化シリコンやPSG等を用いて形成され
る。)とバリアメタル層23(Ti/TiN等を用いて
形成される。)との密着性はあまり良好ではなく、ボン
ディングパッドのサイズが減少すると密着性はより低下
する。したがって、ワイアボンディング時のダメ―ジ等
により、バリアメタル層23/アルミニウム層24がは
がれやすくなり、信頼性の低下を招くという問題点があ
った。
However, in general, the interlayer insulating layer 22 (formed by using silicon oxide, PSG or the like) and the barrier metal layer 23 (formed by using Ti / TiN or the like). Adhesion with is not so good, and as the size of the bonding pad is reduced, the adhesion is further reduced. Therefore, there is a problem in that the barrier metal layer 23 / aluminum layer 24 is easily peeled off due to a failure during wire bonding, leading to a decrease in reliability.

【0004】本願に係わる発明の目的は、ボンディング
パッド部における膜はがれを防止することが可能な半導
体装置を提供することである。
An object of the present invention is to provide a semiconductor device capable of preventing film peeling in a bonding pad portion.

【0005】[0005]

【課題を解決するための手段】本願に係わる半導体装置
は、半導体基板の主面側に形成された第1絶縁層と、上
記第1絶縁層に接する第1導電層と、上記第1絶縁層上
に形成され開口部を有する第2絶縁層と、上記開口部に
おいて上記第1導電層に接する第2導電層と、上記第2
導電層に接しボンディングワイアの接続端子となる第3
導電層とを有するものである。
According to another aspect of the present invention, there is provided a semiconductor device including a first insulating layer formed on a main surface side of a semiconductor substrate, a first conductive layer in contact with the first insulating layer, and the first insulating layer. A second insulating layer formed on the upper surface and having an opening; a second conductive layer in contact with the first conductive layer in the opening;
The third that is in contact with the conductive layer and serves as the connection terminal of the bonding wire
And a conductive layer.

【0006】[0006]

【実施例】図1は、第1実施例を示したものであり、半
導体装置のボンディングパッド部の構成を示したもので
ある。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment and shows the structure of a bonding pad portion of a semiconductor device.

【0007】11はシリコン基板である。12は第1絶
縁層(層厚500〜1000nm程度)であり、LOC
OS構造の素子分離層(構成材料は酸化シリコン)や層
間絶縁層(構成材料は酸化シリコン、PSG、BPSG
等)で構成される。
Reference numeral 11 is a silicon substrate. Reference numeral 12 is a first insulating layer (layer thickness of about 500 to 1000 nm), which is LOC
Element isolation layer of OS structure (constituent material is silicon oxide) and interlayer insulating layer (constituent material is silicon oxide, PSG, BPSG)
Etc.).

【0008】13は第1導電層(層厚200〜400n
m程度)であり、MOSトランジスタのゲ―ト電極(構
成材料はポリシリコン等)と同一材料および同一工程
で、あるいは多層配線の1層めの配線(構成材料はAl
(アルミニウム)等)と同一材料および同一工程で形成
される。
Reference numeral 13 denotes a first conductive layer (layer thickness 200 to 400 n).
m) and the same material and process as the gate electrode of the MOS transistor (the constituent material is polysilicon etc.), or the first layer of the multilayer wiring (the constituent material is Al).
(Aluminum) and the like) and the same process.

【0009】14は第2絶縁層(層厚500〜1000
nm程度)であり、層間絶縁層(構成材料は酸化シリコ
ン、PSG、BPSG等)で構成される。この第2絶縁
層14には開口部14a(一辺の長さは100μm程
度)が形成されている。
Reference numeral 14 denotes a second insulating layer (layer thickness 500 to 1000).
and the interlayer insulating layer (constituent material is silicon oxide, PSG, BPSG, etc.). The second insulating layer 14 has an opening 14a (each side length is about 100 μm).

【0010】15は第2導電層(層厚100nm程度)
であり、MOSトランジスタのソ―ス・ドレイン用コン
タクトのバリアメタル層(Ti(チタン)、W(タング
ステン)、Mo(モリブデン)等の高融点金属あるいは
Ti/TiN等の積層構造を用いて構成される。)と同
一材料および同一工程で形成される。16は第3導電層
(層厚500〜1000nm程度)であり、MOSトラ
ンジスタのソ―ス/ドレイン用コンタクトのバリアメタ
ル層上のソ―ス・ドレイン電極(Al、Al−Si、A
l−Cu、Al−Cu−Si等が用いられる。)と同一
材料および同一工程で形成される。すなわち、第2導電
層15および第3導電層16は、MOSトランジスタの
ソ―ス・ドレイン用コンタクトのバリアメタル層/ソ―
ス・ドレイン電極のパタ―ニングと同時にパタ―ニング
されるわけである。第2導電層15および第3導電層1
6は第2絶縁層14の開口部14aに対応して形成さ
れ、第2導電層15の下面は第1導電層13の上面に接
している。第3導電層16はボンディングワイアの接続
端子となる。
Reference numeral 15 is a second conductive layer (layer thickness of about 100 nm)
The barrier metal layer of the source / drain contact of the MOS transistor (high melting point metal such as Ti (titanium), W (tungsten), Mo (molybdenum) or a laminated structure of Ti / TiN is used. The same material and the same process as the above). Reference numeral 16 denotes a third conductive layer (layer thickness of about 500 to 1000 nm), which is a source / drain electrode (Al, Al-Si, A) on the barrier metal layer of the source / drain contact of the MOS transistor.
1-Cu, Al-Cu-Si, or the like is used. ) And the same material and the same process. That is, the second conductive layer 15 and the third conductive layer 16 are the barrier metal layer / source of the source / drain contact of the MOS transistor.
This is done simultaneously with the patterning of the drain electrode. Second conductive layer 15 and third conductive layer 1
6 is formed corresponding to the opening 14a of the second insulating layer 14, and the lower surface of the second conductive layer 15 is in contact with the upper surface of the first conductive layer 13. The third conductive layer 16 serves as a connection terminal of the bonding wire.

【0011】17は保護絶縁層(層厚1000nm程
度)であり、窒化シリコン、PSG、BPSG等を用い
て形成されている。
Reference numeral 17 is a protective insulating layer (layer thickness of about 1000 nm), which is formed using silicon nitride, PSG, BPSG or the like.

【0012】以上の第1実施例では、第1絶縁層12と
この第1絶縁層12に対して密着性の悪い第2導電層1
5との間に、第1絶縁層12に対して密着性のよい第1
導電層13を設けたので、結果として第1絶縁層12と
第2導電層15との第1導電層13を介しての密着性が
向上する。したがって、ワイアボンディング時のダメ―
ジ等による第2導電層15/第3導電層16の膜はがれ
を防止することが可能となる。
In the first embodiment described above, the first insulating layer 12 and the second conductive layer 1 having poor adhesion to the first insulating layer 12 are used.
Between the first insulating layer 12 and the first insulating layer 12
Since the conductive layer 13 is provided, as a result, the adhesion between the first insulating layer 12 and the second conductive layer 15 via the first conductive layer 13 is improved. Therefore, it is not possible to use wire bonding.
It is possible to prevent the film peeling of the second conductive layer 15 / third conductive layer 16 due to a phenomenon such as a dip.

【0013】また、第1導電層13を設けたことによ
り、その分ボンディングパッド部の層厚が増加するの
で、ワイアボンディング時のダメ―ジを緩和することが
可能となる。
Further, since the first conductive layer 13 is provided, the layer thickness of the bonding pad portion is correspondingly increased, so that the damage at the time of wire bonding can be alleviated.

【0014】図2および図3は、第2実施例を示したも
のである。基本的な構成は図1に示した第1実施例と同
様であるため、実質的に同一の構成要素には同一番号を
付し、説明を省略する。なお、図3では、第2絶縁層1
4および開口部14aのみ示し、その他は省略してい
る。
2 and 3 show a second embodiment. Since the basic configuration is similar to that of the first embodiment shown in FIG. 1, substantially the same components are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 3, the second insulating layer 1
4 and the opening 14a are shown, and others are omitted.

【0015】本第2実施例では、第2絶縁層14の開口
部14aをボンディングパッド部に複数設け、第1導電
層13と第2導電層15との密着性の向上をさらにはか
ったものである。開口部14aのサイズや間隔を適当に
調整することにより、第1導電層13と第2導電層15
との密着性を適宜調整することが可能となる。
In the second embodiment, a plurality of openings 14a of the second insulating layer 14 are provided in the bonding pad portion to further improve the adhesion between the first conductive layer 13 and the second conductive layer 15. is there. The first conductive layer 13 and the second conductive layer 15 can be formed by appropriately adjusting the size and spacing of the openings 14a.
It is possible to appropriately adjust the adhesion to.

【0016】いうまでもないが、本第2実施例において
も第1実施例と同様の効果を奏することが可能である。
Needless to say, the same effects as in the first embodiment can be obtained in the second embodiment.

【0017】[0017]

【発明の効果】本願に係わる発明では、第1絶縁層と第
2導電層との間に第1導電層を設けたので、第1導電層
として第1絶縁層に対して密着性のよい層を用いること
ができ、第1絶縁層と第2導電層との第1導電層を介し
ての密着性を向上させることが可能となる。したがっ
て、ワイアボンディング時のダメ―ジ等による膜はがれ
を防止することが可能となる。
According to the invention of the present application, since the first conductive layer is provided between the first insulating layer and the second conductive layer, a layer having good adhesion to the first insulating layer as the first conductive layer. Can be used, and the adhesion between the first insulating layer and the second conductive layer via the first conductive layer can be improved. Therefore, it is possible to prevent film peeling due to damage or the like during wire bonding.

【図面の簡単な説明】[Brief description of drawings]

【図1】本願に係わる発明の第1実施例を示した説明図FIG. 1 is an explanatory diagram showing a first embodiment of the invention related to the present application.

【図2】本願に係わる発明の第2実施例を示した説明図FIG. 2 is an explanatory view showing a second embodiment of the invention related to the present application.

【図3】本願に係わる発明の第2実施例を示した説明図FIG. 3 is an explanatory view showing a second embodiment of the invention related to the present application.

【図4】従来例を示した説明図FIG. 4 is an explanatory diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

11……半導体基板 12……第1絶縁層 13……第1導電層 14……第2絶縁層 14a…開口部 15……第2導電層 16……第3導電層 11 ... Semiconductor substrate 12 ... 1st insulating layer 13 ... 1st conductive layer 14 ... 2nd insulating layer 14a ... Opening part 15 ... 2nd conductive layer 16 ... 3rd conductive layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の主面側に形成された第1絶
縁層と、 上記第1絶縁層に接する第1導電層と、 上記第1絶縁層上に形成され開口部を有する第2絶縁層
と、 上記開口部において上記第1導電層に接する第2導電層
と、 上記第2導電層に接しボンディングワイアの接続端子と
なる第3導電層とを有する半導体装置。
1. A first insulating layer formed on the main surface side of a semiconductor substrate, a first conductive layer in contact with the first insulating layer, and a second insulating layer formed on the first insulating layer and having an opening. A semiconductor device having a layer, a second conductive layer in contact with the first conductive layer in the opening, and a third conductive layer in contact with the second conductive layer and serving as a connection terminal of a bonding wire.
JP997395A 1995-01-25 1995-01-25 Semiconductor device Pending JPH08203952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP997395A JPH08203952A (en) 1995-01-25 1995-01-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP997395A JPH08203952A (en) 1995-01-25 1995-01-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH08203952A true JPH08203952A (en) 1996-08-09

Family

ID=11734869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP997395A Pending JPH08203952A (en) 1995-01-25 1995-01-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH08203952A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417568B1 (en) 1999-03-12 2002-07-09 Nec Corporation Semiconductor device
JP2006165515A (en) * 2004-11-11 2006-06-22 Denso Corp Semiconductor device and its manufacturing method
WO2015068439A1 (en) * 2013-11-11 2015-05-14 トヨタ自動車株式会社 Electrode body
CN113437139A (en) * 2020-03-23 2021-09-24 三菱电机株式会社 Semiconductor device with a plurality of semiconductor chips

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58106841A (en) * 1981-12-18 1983-06-25 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58106841A (en) * 1981-12-18 1983-06-25 Hitachi Ltd Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417568B1 (en) 1999-03-12 2002-07-09 Nec Corporation Semiconductor device
JP2006165515A (en) * 2004-11-11 2006-06-22 Denso Corp Semiconductor device and its manufacturing method
JP4674522B2 (en) * 2004-11-11 2011-04-20 株式会社デンソー Semiconductor device
WO2015068439A1 (en) * 2013-11-11 2015-05-14 トヨタ自動車株式会社 Electrode body
CN113437139A (en) * 2020-03-23 2021-09-24 三菱电机株式会社 Semiconductor device with a plurality of semiconductor chips
US11410946B2 (en) 2020-03-23 2022-08-09 Mitsubishi Electric Corporation Semiconductor apparatus

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