JPH05218125A - Structure of bonding pad - Google Patents
Structure of bonding padInfo
- Publication number
- JPH05218125A JPH05218125A JP4022317A JP2231792A JPH05218125A JP H05218125 A JPH05218125 A JP H05218125A JP 4022317 A JP4022317 A JP 4022317A JP 2231792 A JP2231792 A JP 2231792A JP H05218125 A JPH05218125 A JP H05218125A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- aluminum
- insulating film
- layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置におけるボ
ンディングパッドの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a bonding pad in a semiconductor device.
【０００２】[0002]
【従来の技術】従来のパワーＭＯＳＦＥＴのボンディン
グパッドの構造を図面を参照して説明する。2. Description of the Related Art The structure of a conventional bonding pad of a power MOSFET will be described with reference to the drawings.
【０００３】元来、パワーＭＯＳＦＥＴのソースボンデ
ィングパッドは図３の断面図のように、アルミ１とシリ
コン４が全面で接触するようになっていた。しかし、パ
ワーＭＯＳＦＥＴのボンディングワイヤは大電力用で太
いため、そのボンディングパッドも大きく、ソースボン
ディングパッド下にセルがない分、ＲＯＮ特性（素子を
縦方向に流れる抵抗）が高くなる。Originally, the source bonding pad of the power MOSFET was designed so that the aluminum 1 and the silicon 4 were in contact with each other over the entire surface as shown in the sectional view of FIG. However, since the bonding wire of the power MOSFET is large for high power and has a large thickness, its bonding pad is also large, and since there is no cell under the source bonding pad, the RON characteristic (resistance flowing in the element in the vertical direction) is high.
【０００４】そこで、図４（ａ）のソースボンディング
パッドの平面図，図４（ｂ）の（ａ）図の点線Ａ−Ａに
沿う断面図のように、ソースボンディングパッド下にセ
ルをいれる構造になってきている。ここで、１はアル
ミ，３はゲートポリシリコン，４はシリコン，５はコン
タクトホール，６は絶縁酸化膜である。１つのセルはゲ
ートポリシリコンとコンタクトホールのパターンででき
ており、これが図４（ａ）の平面図のように整列して配
置されている。また、図４（ｂ）の断面図のように、ゲ
ートポリシリコン３は絶縁酸化膜６に覆われており、ア
ルミ１やシリコン４とは絶縁分離されている。またアル
ミ１はコンタクトホール５において、ソース（図示せ
ず）に接続する。そしてボンディングワイヤの接続はア
ルミ１の上に付けるようになっていた。Therefore, as shown in the plan view of the source bonding pad of FIG. 4A and the sectional view taken along the dotted line A--A of FIG. 4B, the cell is placed under the source bonding pad. Is becoming. Here, 1 is aluminum, 3 is gate polysilicon, 4 is silicon, 5 is a contact hole, and 6 is an insulating oxide film. One cell has a pattern of gate polysilicon and contact holes, which are aligned and arranged as in the plan view of FIG. Further, as shown in the sectional view of FIG. 4B, the gate polysilicon 3 is covered with the insulating oxide film 6, and is insulated from the aluminum 1 and the silicon 4. The aluminum 1 is connected to the source (not shown) in the contact hole 5. Then, the bonding wire was connected on the aluminum 1.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記の
ボンディングパッド構造では、コンタクトホールのアル
ミ１は表面が他の部分（ゲートポリシリコン３の上）よ
り低くなっているので、ボンディングワイヤを固着接続
する時に高い部分において下方向への力がかかるため、
ゲートポリシリコン３のコンタクトホール５側端部上の
アルミ１がコンタクトホールに向かって流れ、そのため
同部分の絶縁酸化膜が破壊され、ゲート−ソース間ショ
ートや耐圧不良が発生することがあった。However, in the above-mentioned bonding pad structure, the surface of the aluminum 1 of the contact hole is lower than that of the other portion (on the gate polysilicon 3), so that the bonding wire is fixedly connected. Sometimes a high downward force is applied,
The aluminum 1 on the end portion of the gate polysilicon 3 on the side of the contact hole 5 flows toward the contact hole, so that the insulating oxide film in the same portion is destroyed, which may cause a gate-source short circuit or a breakdown voltage failure.
【０００６】[0006]
【課題を解決するための手段】この発明は上記の課題を
解決するために、半導体基板上に導電層を有し、前記導
電層上に絶縁膜を介して他の電極のボンディングパッド
部である金属層を有し、前記金属層はボンディングパッ
ド部で前記導電層に近接するコンタクトホールを介し
て、前記半導体基板に接続するボンディングパッドの構
造において、前記金属層を層間絶縁膜を介する金属２層
にしたことを特徴とするボンディングパッドの構造を特
徴とする。In order to solve the above problems, the present invention is a bonding pad portion of another electrode having a conductive layer on a semiconductor substrate and an insulating film on the conductive layer. In a structure of a bonding pad having a metal layer, the metal layer being connected to the semiconductor substrate via a contact hole adjacent to the conductive layer at a bonding pad portion, the metal layer is a metal two layer via an interlayer insulating film. The structure of the bonding pad is characterized in that
【０００７】[0007]
【作用】上記の構成によると、金属と金属の間にある層
間膜が、ボンディングワイヤを固着接続する時の下方向
の力の衝撃を吸収するように作用し、絶縁膜が破壊され
ずワイヤボンディング時のショートや耐圧不良をなくす
ことができる。According to the above construction, the interlayer film between the metals acts to absorb the impact of the downward force when the bonding wire is fixedly connected, and the insulating film is not destroyed and the wire bonding is performed. It is possible to eliminate short-circuiting and withstand voltage failure.
【０００８】[0008]
【実施例】以下、この発明について図面を参照して説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【０００９】図１はこの発明の第１実施例のパワーＭＯ
ＳＦＥＴのボンディングパッドの断面図である。図にお
いて１はアルミ，２は第２アルミ，３はゲートポリシリ
コン，４はシリコン基板，５はコンタクトホール，６は
ＳｉＯ2 でなる絶縁膜，７は層間酸化膜である。FIG. 1 shows the power MO of the first embodiment of the present invention.
It is sectional drawing of the bonding pad of SFET. In the figure, 1 is aluminum, 2 is second aluminum, 3 is gate polysilicon, 4 is a silicon substrate, 5 is a contact hole, 6 is an insulating film made of SiO 2 , and 7 is an interlayer oxide film.
【００１０】次に製造方法をともなって構造の説明をす
る。まず、本来のアルミ１を蒸着で形成し、ＰＲでパタ
ーニングした後、全面に層間酸化膜７を成長させＰＲで
パターニングをし、ボンディングパッド部にのみ残す。
次に第２アルミ２を蒸着で形成し、前記のボンディング
パッド５の層間酸化膜７より広い面積でアルミをＰＲパ
ターニングで残すと、図１のようになる。Next, the structure will be described with the manufacturing method. First, the original aluminum 1 is formed by vapor deposition and patterned by PR, then an interlayer oxide film 7 is grown on the entire surface and patterned by PR, and left only on the bonding pad portion.
Next, the second aluminum 2 is formed by vapor deposition, and the aluminum is left in a larger area than the interlayer oxide film 7 of the bonding pad 5 by the PR patterning, as shown in FIG.
【００１１】この実施例によれば、アルミ１と第２アル
ミ２の間にある層間酸化膜７がワイヤボンディング時の
下方向の力の衝撃をかなり吸収するため、特性不良が発
生しないという利点がある。According to this embodiment, the interlayer oxide film 7 located between the aluminum 1 and the second aluminum 2 absorbs a shock of a downward force during wire bonding, so that there is an advantage that characteristic defects do not occur. is there.
【００１２】[0012]
【実施例２】図２はこの発明の第２実施例のパワーＭＯ
ＳＦＥＴのボンディングパッドの断面図である。図２に
おいて８は層間窒化膜，９はスルーホールである。この
実施例は前記第１の実施例の層間酸化膜７が層間窒化膜
８に変わったこと，さらにスルーホール９を設けた点を
除いては第１の実施例と同様であるため、同一部分には
同一参照符号を付してその説明を省略する。この実施例
では層間窒化膜８を衝撃吸収材として使うことのほか
に、スルーホール９を作ることにより、さらに抵抗を小
さくできるという利点がある。Second Embodiment FIG. 2 shows a power MO according to a second embodiment of the present invention.
It is sectional drawing of the bonding pad of SFET. In FIG. 2, 8 is an interlayer nitride film and 9 is a through hole. This embodiment is the same as the first embodiment except that the interlayer oxide film 7 of the first embodiment is changed to the interlayer nitride film 8 and the through hole 9 is provided. Are assigned the same reference numerals and explanations thereof are omitted. In this embodiment, in addition to using the interlayer nitride film 8 as a shock absorbing material, the through hole 9 is formed, which has the advantage that the resistance can be further reduced.
【００１３】[0013]
【発明の効果】以上、説明したように、この発明は層間
膜をつけたことにより、ボンディングワイヤを固着接続
するときの衝撃力が緩和され、特性不良をなくすことが
できる効果がある。As described above, according to the present invention, by providing the interlayer film, the impact force at the time of fixing and connecting the bonding wire is mitigated, and the characteristic defect can be eliminated.
【図１】 この発明にかかる一実施例のパワーＭＯＳＦ
ＥＴのソース電極のボンディングパッドの断面図FIG. 1 is a power MOSF according to an embodiment of the present invention.
Cross-sectional view of bonding pad of source electrode of ET
【図２】 この発明にかかる他の実施例におけるパワー
ＭＯＳＦＥＴのソース電極のボンディングパッドの断面
図FIG. 2 is a sectional view of a bonding pad of a source electrode of a power MOSFET according to another embodiment of the present invention.
【図３】 従来のパワーＭＯＳＦＥＴのボンディングパ
ッドの断面図FIG. 3 is a sectional view of a conventional power MOSFET bonding pad.
【図４】（ａ） 従来の他の例のパワーＭＯＳＦＥＴの
ソース電極のボンディングパッドの平面図 （ｂ） 図（ａ）のＡ−Ａ線に沿う断面図FIG. 4A is a plan view of a bonding pad of a source electrode of a power MOSFET of another conventional example. FIG. 4B is a sectional view taken along line AA of FIG.
１ アルミ ２ 第２アルミ ３ ゲートポリシリコン ４ シリコン基板 ５ コンタクトホール ６ ＳｉＯ2 でなる絶縁膜 ７ 層間酸化膜 ８ 層間窒化膜 ９ スルーホール1 Aluminum 2 Second Aluminum 3 Gate Polysilicon 4 Silicon Substrate 5 Contact Hole 6 Insulating Film Made of SiO 2 7 Interlayer Oxide Film 8 Interlayer Nitride Film 9 Through Hole
Claims (3)
上に絶縁膜を介して他の電極のボンディングパッド部で
ある金属層を有し、前記金属層はボンディングパッド部
で前記導電層に近接するコンタクトホールを介して、前
記半導体基板に接続するボンディングパッドの構造にお
いて、前記金属層を層間絶縁膜を介する金属２層にした
ことを特徴とするボンディングパッドの構造。1. A conductive layer is provided on a semiconductor substrate, and a metal layer, which is a bonding pad portion of another electrode, is provided on the conductive layer via an insulating film, and the metal layer is conductive at the bonding pad portion. A structure of a bonding pad connected to the semiconductor substrate via a contact hole adjacent to the layer, wherein the metal layer is a two-layer metal via an interlayer insulating film.
ルーホールを介して接続したことを特徴とする請求項１
記載のボンディングパッドの構造。2. The upper and lower two metal layers are connected to each other through a through hole of an interlayer insulating film.
Bonding pad structure described.
がソース電極であるパワーＭＯＳＦＥＴのボンディング
パッドの構造。3. A structure of a bonding pad of a power MOSFET in which the conductive layer is a gate and the other electrode is a source electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4022317A JPH05218125A (en) | 1992-02-07 | 1992-02-07 | Structure of bonding pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4022317A JPH05218125A (en) | 1992-02-07 | 1992-02-07 | Structure of bonding pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218125A true JPH05218125A (en) | 1993-08-27 |
Family
ID=12079353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4022317A Pending JPH05218125A (en) | 1992-02-07 | 1992-02-07 | Structure of bonding pad |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218125A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100423532B1 (en) * | 2001-06-27 | 2004-03-18 | 주식회사 하이닉스반도체 | Method for forming bonding pad of semiconductor |
| JP2007042817A (en) * | 2005-08-02 | 2007-02-15 | Sanyo Electric Co Ltd | Insulated-gate semiconductor device and its manufacturing method |
-
1992
- 1992-02-07 JP JP4022317A patent/JPH05218125A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100423532B1 (en) * | 2001-06-27 | 2004-03-18 | 주식회사 하이닉스반도체 | Method for forming bonding pad of semiconductor |
| JP2007042817A (en) * | 2005-08-02 | 2007-02-15 | Sanyo Electric Co Ltd | Insulated-gate semiconductor device and its manufacturing method |
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