JPS61144050A - Protective circuit for input to semiconductor integrated circuit device - Google Patents
Protective circuit for input to semiconductor integrated circuit deviceInfo
- Publication number
- JPS61144050A JPS61144050A JP26795384A JP26795384A JPS61144050A JP S61144050 A JPS61144050 A JP S61144050A JP 26795384 A JP26795384 A JP 26795384A JP 26795384 A JP26795384 A JP 26795384A JP S61144050 A JPS61144050 A JP S61144050A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistors
- semiconductor integrated
- input
- protection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 230000001681 protective effect Effects 0.000 title abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000000126 substance Substances 0.000 abstract 2
- 230000004927 fusion Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000007664 blowing Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路装置（以下ＩＣという）の
入力保護回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input protection circuit for a semiconductor integrated circuit device (hereinafter referred to as an IC).
第３図は従来のＩＣの入力保護回路のレイ７’７トを示
す図である。この図におい工、１はアルミ配線層による
外部入力端子、２はポリシリコン層で形成され、一端が
外部入力端子１に接続され。FIG. 3 is a diagram showing the layout of a conventional IC input protection circuit. In this figure, 1 is an external input terminal formed of an aluminum wiring layer, 2 is formed of a polysilicon layer, and one end is connected to the external input terminal 1.
他端が内部回路の入力となるノードＮに接続された保護
用の抵抗体、３はグランド配線、４はドレインがノード
ＮＫ接続され、ゲートとソースがグランド配線３に接続
されたＭＯＳトランジスタであり、Ｃはコレクタ部分、
Ｄは拡散領域を示す。The other end is a protective resistor connected to a node N which is the input of the internal circuit, 3 is a ground wire, 4 is a MOS transistor whose drain is connected to the node NK, and whose gate and source are connected to the ground wire 3. , C is the collector part,
D indicates the diffusion region.
第４図は第３図に示す入力保護回路の等価回路図であり
、第４図の符号１〜４は第３図と同じものを示す。第４
図の５は配線容量および内部回路のゲート容量等を含め
たノードＮの浮遊容量である。FIG. 4 is an equivalent circuit diagram of the input protection circuit shown in FIG. 3, and numerals 1 to 4 in FIG. 4 indicate the same parts as in FIG. 3. Fourth
5 in the figure is the stray capacitance of the node N, including the wiring capacitance and the gate capacitance of the internal circuit.
従来のＩＣの入力保護回路は上記のようＫｍ成され、外
部入力端子１にサージ電圧が印加された場合、抵抗体２
と浮遊容量５との時定数によつ工。The input protection circuit of the conventional IC is constructed as described above, and when a surge voltage is applied to the external input terminal 1, the resistor 2
It is calculated by the time constant of 5 and the stray capacitance.
ノードＮの電圧は外部入力端子１に比べてゆるやかに上
昇する。そして、ノードＮの電圧があるレベル以上にな
ると、パンチスルーによってＭＯＳトランジスタ４を介
し１電流が流れ、抵抗体２による電圧降下が起り、サー
ジ電圧が内部回路に達することを防止する。The voltage at node N rises more slowly than at external input terminal 1. When the voltage at node N exceeds a certain level, one current flows through MOS transistor 4 due to punch-through, and a voltage drop occurs due to resistor 2, preventing the surge voltage from reaching the internal circuit.
上記のような従来の入力保護回路では、サージ電圧が外
部入力端子１に印加されたとき、抵抗体２において熱が
発生し、充分大きなエネルギーを持つサージに対しては
、抵抗体２が溶断されるという問題点があった。また、
溶断されＫ＜くするために抵抗体２を太くすると、抵抗
値を確保するため忙抵抗体２を長くする必要が生じ、抵
抗体２を形成するための面積が増大するという問題点も
あった。In the conventional input protection circuit as described above, when a surge voltage is applied to the external input terminal 1, heat is generated in the resistor 2, and the resistor 2 is blown out by a surge with sufficiently large energy. There was a problem that Also,
If the resistor 2 is made thicker in order to prevent K< from being fused, it becomes necessary to make the resistor 2 longer in order to secure the resistance value, and there is also the problem that the area for forming the resistor 2 increases. .
この発明各文、かかる問題点を解決するためＫなされた
もので、サージ耐圧が充分に高いＩＣの入力保護回路を
得ることを目的とする。The present invention has been made to solve these problems, and an object thereof is to obtain an input protection circuit for an IC having a sufficiently high surge withstand voltage.
この発明に係るＩＣの入力保護回路は、一端が外部入力
端子に接続され、他端が内部回路に接続された入力保護
回路を構成する抵抗体に対して、この抵抗体よりも熱抵
抗の低い物質で形成される放熱板を抵抗体に接触するよ
うに配置したものである。The input protection circuit for an IC according to the present invention has a thermal resistance lower than that of the resistor that constitutes the input protection circuit, one end of which is connected to an external input terminal and the other end of which is connected to an internal circuit. A heat sink made of a material is placed in contact with a resistor.
この発明においＣは、大きなエネルギーを有する入力サ
ージに対して、放熱部を構成している抵抗体と、この抵
抗体に接触して配置した放熱板とｋより熱エネルギーを
放散させる。In this invention, C dissipates thermal energy from a resistor forming a heat dissipating section and a heat dissipating plate disposed in contact with the resistor in response to an input surge having large energy.
第１図はこの発明の一実施例を示したＩＣの入力保護回
路のレイアワトを示す図であり、符号１〜４は第３図と
同じものであり、６は前記抵抗体２に付加された放熱板
であり、アルミ配線層のような抵抗体よりも熱抵抗が低
い物質で形成されている。第２図は第１図のＡ−に＃ｊ
Ｋおける断面図であり、符号２．６は第１図と同じもの
を示し、７は半導体基板、８は酸化膜、９はポリシリコ
ン層とアルミ配線層の間の層間絶縁膜、１０はチップ保
護膜である。FIG. 1 is a diagram showing the layout of an input protection circuit of an IC showing an embodiment of the present invention, where numerals 1 to 4 are the same as in FIG. 3, and 6 is a diagram added to the resistor 2. It is a heat sink and is made of a material that has lower thermal resistance than a resistor such as an aluminum wiring layer. Figure 2 is #j at A- in Figure 1.
2.6 is the same as in FIG. 1, 7 is a semiconductor substrate, 8 is an oxide film, 9 is an interlayer insulating film between a polysilicon layer and an aluminum wiring layer, and 10 is a chip. It is a protective film.
上記のように構成されたＩＣの入力保護回路においては
、抵抗体２から発生する熱は抵抗体２よりもチップ表面
近くに位置し１表面積の大きいアルミ配＠による放熱板
６によって効率よく放熱されるＣ′！！た。アルミ配線
による放熱板６を第１図に示すよ５に配置すれば、抵抗
体２の電気的抵抗は殆んど低下しないので、抵抗体２の
長さを従来よりも長くする必要はない。゛したがって１
面積をあまり増大させることなく、抵抗体２の溶断を防
ぐことができる。In the IC input protection circuit configured as described above, the heat generated from the resistor 2 is efficiently dissipated by the aluminum heat sink 6 which is located closer to the chip surface than the resistor 2 and has a large surface area. C'! ! Ta. If the heat sink 6 made of aluminum wiring is arranged at 5 as shown in FIG. 1, the electrical resistance of the resistor 2 will hardly decrease, so there is no need to make the length of the resistor 2 longer than before.゛Thus 1
It is possible to prevent the resistor 2 from blowing out without significantly increasing its area.
なお、上記実施例では、抵抗体２にポリシリコンを用い
、放熱板６ｓｃアルミ配線を用いたが、他の物質の組合
わせであつ（もよい。In the above embodiment, polysilicon was used for the resistor 2 and aluminum wiring was used for the heat sink 6sc, but combinations of other materials may also be used.
この発明は以上説明したとおり、一端が外部入力端子に
接続され、他端が内部回路に接続された抵抗体と、この
抵抗体よりも熱抵抗が低い物質で形成され、かつ前記抵
抗体に接触するように配置された放熱板とを備えている
ので、放熱が十分に行われ、サージ耐圧の大きなＩＣの
入力保護回路が得られる効果がある。As explained above, this invention includes a resistor whose one end is connected to an external input terminal and the other end is connected to an internal circuit, and which is made of a material having a lower thermal resistance than the resistor and is in contact with the resistor. Since the heat dissipation plate is arranged in such a manner that heat dissipation is performed sufficiently, it is possible to obtain an input protection circuit for an IC having a high surge withstand voltage.
第１図はこの発明の一実施例によるＩＣの入力保護回路
のレイアワト図、第２図は第１図Ａ −Ａ’線における
断面図、第３図は従来１のＩＣの入力保護回路のレイフ
ット図、第４図は第３図の入力保護回路の等価回路図で
ある。
図において、１は外部入力端子、２は抵抗体。
３はグランド配線、−はＭＯＳ）ランジスタ、５は浮遊
容量、６は放熱板、１は半導体基板、８は酸化膜、９は
眉間絶縁膜、１０はチップ保護膜である。
なお、各図中同一符号は同一または相当部分を示す＠
代理人 大岩増雄 （外２名）
第１図
第２図
第３図
第４図FIG. 1 is a layout diagram of an input protection circuit of an IC according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A' in FIG. 4 is an equivalent circuit diagram of the input protection circuit of FIG. 3. In the figure, 1 is an external input terminal and 2 is a resistor. 3 is a ground wiring, - is a MOS transistor, 5 is a stray capacitance, 6 is a heat sink, 1 is a semiconductor substrate, 8 is an oxide film, 9 is an insulating film between the eyebrows, and 10 is a chip protection film. In addition, the same reference numerals in each figure indicate the same or corresponding parts @ Agent: Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure 4
Claims (2)
に接続された抵抗体と、前記抵抗体よりも熱抵抗が低い
物質で形成され、かつ前記抵抗体に接触するように配置
された放熱板とを備えたことを特徴とする半導体集積回
路装置の入力保護回路。(1) A resistor having one end connected to an external input terminal and the other end connected to an internal circuit, and a resistor made of a material having a lower thermal resistance than the resistor and arranged so as to be in contact with the resistor. 1. An input protection circuit for a semiconductor integrated circuit device, comprising a heat sink.
ルミ配線層で形成されたことを特徴とする特許請求の範
囲第（１）項記載の半導体集積回路装置の入力保護回路
。(2) The input protection circuit for a semiconductor integrated circuit device according to claim (1), wherein the resistor is formed of a polysilicon layer and the heat sink is formed of an aluminum wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26795384A JPS61144050A (en) | 1984-12-17 | 1984-12-17 | Protective circuit for input to semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26795384A JPS61144050A (en) | 1984-12-17 | 1984-12-17 | Protective circuit for input to semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61144050A true JPS61144050A (en) | 1986-07-01 |
Family
ID=17451888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26795384A Pending JPS61144050A (en) | 1984-12-17 | 1984-12-17 | Protective circuit for input to semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61144050A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5500553A (en) * | 1992-08-12 | 1996-03-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
-
1984
- 1984-12-17 JP JP26795384A patent/JPS61144050A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5500553A (en) * | 1992-08-12 | 1996-03-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
| US5956592A (en) * | 1992-08-12 | 1999-09-21 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
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