JPS6167242A - Wafer accommodating jig - Google Patents
Wafer accommodating jigInfo
- Publication number
- JPS6167242A JPS6167242A JP19086684A JP19086684A JPS6167242A JP S6167242 A JPS6167242 A JP S6167242A JP 19086684 A JP19086684 A JP 19086684A JP 19086684 A JP19086684 A JP 19086684A JP S6167242 A JPS6167242 A JP S6167242A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- jig
- side plate
- grooves
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/67326—Horizontal carrier comprising wall type elements whereby the substrates are vertically supported, e.g. comprising sidewalls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造に用いるウェーハ収容治具
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wafer storage jig used for manufacturing semiconductor devices.
半導体装置の製造に用いる半導体薄板(ウェーハ)はそ
の暇り扱いを容易にするために、洗浄、エツチング、保
管等は収容治具によって取り扱われる。そしてこの収容
治具は使用プロセスによってその材質が使い分けられて
いるの力よ一般的である。従来この種の治具として第2
図に平面図、第3図にその正面図を示すもの力;あった
。図において(1)は収容治具、(2)は収容溝、てこ
の品分にウェーハを収容する。すなわち、第4図は第2
図の■−■線での断面図で、一点鎖線で示したウェーノ
ー(3)が図示のように収容される。To facilitate the handling of semiconductor thin plates (wafers) used in the manufacture of semiconductor devices, cleaning, etching, storage, etc. are handled using storage jigs. This storage jig is generally made of different materials depending on the process of use. Conventionally, this is the second jig of this type.
Figure 3 shows a plan view, and Figure 3 shows its front view. In the figure, (1) is a storage jig, (2) is a storage groove, and a wafer is stored in a lever item. In other words, Figure 4 is
In the cross-sectional view taken along the line ■-■ in the figure, the Waeno (3) indicated by the dashed line is accommodated as shown.
この収容治具(1)を用いてその中に収容し九ウェーハ
(3)の洗浄および乾燥を行なうのであるカニ、洗浄後
の乾燥作業では収容治具(1)全体を伊1えば100゜
r、p、 m、で高速回転させ、収容治具(1)内のウ
ェーノ1(3)を乾燥させている。This housing jig (1) is used to clean and dry the nine wafers (3) housed in it.During the drying work after cleaning, the entire housing jig (1) is heated to an angle of 100 degrees, for example. , p, m, to dry the wafer 1 (3) in the storage jig (1).
このような収容治具(1)は樹脂系の絶縁物で構成され
ているので、高速回転時の空気との摩擦で静電気が発生
し帯電する。そして、これによって周囲に浮遊している
塵埃などの異物や;弓1きつけられて収容治具(1)全
体に付着する。Since such a housing jig (1) is made of a resin-based insulator, static electricity is generated due to friction with air during high-speed rotation, and the jig is charged. As a result, foreign matter such as dust floating around the bow 1 is attached and adheres to the entire storage jig (1).
ところで、上述の従来の収容治具(1)に設けられた収
容溝(2)の両側壁はウエーノ(3)の外周部と連続的
に対向して、おり、接触する機会が多く、収容溝(2)
の側壁に付着した異物、塵埃はウエーノ(3)へ付着し
、ウエーノ〜(3)上に形成される半導体素子の不良原
因となるという問題点があった。By the way, both side walls of the accommodation groove (2) provided in the above-mentioned conventional accommodation jig (1) are continuously opposed to the outer circumference of the ueno (3), and there are many opportunities for contact with the outer periphery of the Ueno (3). (2)
There is a problem in that foreign matter and dust attached to the side walls of the wafer (3) adhere to the wafer (3) and cause defects in semiconductor elements formed on the wafer (3).
この発明は以上のような問題点を解決するためになされ
たもので、収容溝の両側壁と当該溝に収容するウエーノ
)外周部との接触の機会が少なく、塵埃などの異物汚染
を与えないウェー/%収容治具を得ることを目的として
いる。This invention was made to solve the above-mentioned problems, and there is little chance of contact between the side walls of the storage groove and the outer periphery of the wafer accommodated in the groove, and there is no possibility of contamination with foreign substances such as dust. The purpose is to obtain a jig that accommodates weight/%.
この発明にかかるウェーノー収容溝具では各収容溝の両
側壁を構成する側板凸条に切り欠き加工を施し、切り欠
き形状側板凸条部を形成したものであるO
〔作用〕
この発明においてはウェーノー収容溝の両側壁板に切9
欠き部を設け 、当該溝に収容されるウ
エーノ1の外周部との接触面積を小さくできるようにし
た。In the waeno storage groove device according to the present invention, the side plate protrusions constituting both side walls of each storage groove are notched to form notch-shaped side plate protrusions. Cut 9 into the wall plates on both sides of the storage groove.
The notch is provided to reduce the contact area with the outer circumference of the ueno 1 accommodated in the groove.
第1図はこの発明の一実施例の構成を示す断面図で、前
述の第2〜4図の従来例と同一符号はり等部分を示す。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, in which parts such as beams are shown with the same reference numerals as those of the conventional example shown in FIGS. 2 to 4 described above.
この実施例も従来例と同様、箱形枠構造をしており、両
側板の相対向する面にそれぞれ互いに灯心して収容溝(
2)が形成され、当然これらの相隣接する溝(2)の相
互間およびfn (2)の形成部の両側には側板凸条部
が形成されている。そして、この実施例の特徴は、ウェ
ーハ収容溝(2)の両側壁を構成する側板凸条部に図示
のように切シ欠き加工を施し、切り欠き形状側板凸条部
(4)を形成した点にある。そして、その加工の程度は
隣接する収容溝(2)に収容されるウェーハ(3)が整
然と保持され、しかも、収容治具(1)の相互間でウェ
ーハ(3)の移し替え、更には、ウェーハ(3)を水平
状態で行うロード、アンロード操作に支障がない範囲で
あればよい。Like the conventional example, this embodiment also has a box-shaped frame structure, and the wicks are centered on each other on the opposing surfaces of both side plates.
2) are formed, and of course side plate protrusions are formed between these adjacent grooves (2) and on both sides of the forming portion of fn (2). The feature of this embodiment is that the side plate protrusions constituting both side walls of the wafer storage groove (2) are notched as shown in the figure to form cutout-shaped side plate protrusions (4). At the point. The degree of processing is such that the wafers (3) housed in adjacent housing grooves (2) are held in an orderly manner, and the wafers (3) can be transferred between the housing jigs (1). It may be within a range that does not interfere with loading and unloading operations performed with the wafer (3) in a horizontal state.
このような構成にしたので、ウェーハ収容時、ウェーハ
移し替え時、ロード、アンロード時の収容溝(2)の側
壁とウェーハ(3)との接触の機会が減少する。With this configuration, the chances of contact between the side wall of the storage groove (2) and the wafer (3) during wafer storage, wafer transfer, loading, and unloading are reduced.
なお、上記実施例では切シ欠き形状凸条部(4)は従来
の凸条部に単に切り欠き加工を施した場合を示したが、
第1図に破線で示したように、凸条部の高さ、幅を適当
に変化させてもよい。In addition, in the above embodiment, the notch-shaped convex strip (4) is a case in which a conventional convex strip is simply cut out,
As shown by broken lines in FIG. 1, the height and width of the protruding stripes may be changed appropriately.
以上説明したように、この発明に係るウエーノ・収容治
具では、相隣接するウエーノ・収容溝相互間及び収容溝
の形成部の両側の側板凸条部を切り欠き形状としたので
、収容するウェーハ周縁部への接触の機会が小さくなり
、ウェーハへの異物汚染を減少させ、半導体素子の製造
歩留シの向上を計れる。As explained above, in the wafer/accommodating jig according to the present invention, the protruding portions of the side plates between adjacent wafer/accommodating grooves and on both sides of the forming portion of the accommodating groove are cut out, so that the wafers to be accommodated are The chance of contact with the periphery is reduced, reducing contamination of foreign substances on the wafer, and improving the manufacturing yield of semiconductor devices.
第1図はこの発明の一実施例の構成を承す断面図、第2
図は従来のものの平面図、第3図はその正面図、第4図
は第2図のF/−M線での断面図であるっ
図において、(1)は収容治具、(2)は収容溝、(3
)はウェーハ、(4)は切り欠き形状側板凸条部である
。
なお、各図中同一符号は同一または相当部分を示す。Fig. 1 is a sectional view showing the configuration of one embodiment of the present invention;
The figure is a plan view of the conventional one, FIG. 3 is a front view thereof, and FIG. 4 is a sectional view taken along the F/-M line in FIG. 2. In the figures, (1) is a storage jig, (2) is the accommodation groove, (3
) is a wafer, and (4) is a notch-shaped side plate protrusion. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
複数の収容溝が形成され、上記両側板の上記各対応する
収容溝にウェーハの周縁部を挿入して上記ウェーハを収
容するものにおいて、相隣接する上記収容溝相互間の上
記側板の凸条部及び上記収容溝の形成部の両側の上記側
板の凸条部を切り欠き形状としたことを特徴とするウェ
ーハ収容治具。(1) A plurality of accommodating grooves are formed in opposing surfaces of both side plates in correspondence with each other, and the wafer is accommodated by inserting the peripheral edge of the wafer into each of the corresponding accommodating grooves of the both side plates. A wafer storage jig, characterized in that the protruding stripes of the side plate between the adjacent accommodation grooves and the protruding stripes of the side plate on both sides of the forming portion of the accommodation groove are cut out.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19086684A JPS6167242A (en) | 1984-09-10 | 1984-09-10 | Wafer accommodating jig |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19086684A JPS6167242A (en) | 1984-09-10 | 1984-09-10 | Wafer accommodating jig |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6167242A true JPS6167242A (en) | 1986-04-07 |
Family
ID=16265064
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19086684A Pending JPS6167242A (en) | 1984-09-10 | 1984-09-10 | Wafer accommodating jig |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6167242A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63159839U (en) * | 1987-04-06 | 1988-10-19 | ||
JPH01127244U (en) * | 1988-02-23 | 1989-08-31 | ||
JPH0278246A (en) * | 1988-09-14 | 1990-03-19 | Kakizaki Seisakusho:Kk | Basket for thin film treatment |
US5278104A (en) * | 1989-07-25 | 1994-01-11 | Kabushiki Kaisha Toshiba | Semiconductor wafer carrier having a dust cover |
-
1984
- 1984-09-10 JP JP19086684A patent/JPS6167242A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63159839U (en) * | 1987-04-06 | 1988-10-19 | ||
JPH01127244U (en) * | 1988-02-23 | 1989-08-31 | ||
JPH0278246A (en) * | 1988-09-14 | 1990-03-19 | Kakizaki Seisakusho:Kk | Basket for thin film treatment |
US5278104A (en) * | 1989-07-25 | 1994-01-11 | Kabushiki Kaisha Toshiba | Semiconductor wafer carrier having a dust cover |
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