JPS6159682A - Variable bit length memory - Google Patents

Abstract

PURPOSE:To use a capacity of a memory efficiently by making variable the number of bits composing the data per address in accordance with necessities. CONSTITUTION:By designating the data of mode designating data signal lines MD0 and MD1, the number of bits per word length is designated and the data on internal control mode lines M0-M2 from a bit length mode designating circuit 16 are designated. In an address converting circuit 17 in accordance with the designated bit length mode, external designating address lines A0-A9 are converted to block enable lines ME0-ME3 of a data memory circuit 18 and internal designating address lines Adr0-Adr7. Adr4-Adr7 designate a line of a memory cell array of respective blocks through a line decoder 2 in the circuit 18, and Adr0-Adr3 designate a row through a row recorder 3, determine the address, the data of the address are read by a sense amplifier/selector which belong to blocks enable by enable lines ME0-ME3 and outputted through a data changing-over circuit 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention provides storage circuits that require two different bit lengths and word lengths, such as a communication path switch memory and a communication path control memory in an electronic exchange, for example, in an 18-bit system. Memo! The present invention relates to such a memory (variable bit length memory) that uses J LSI and can be provided with a memory that only has a simple control circuit added thereto.

[Conventional technology]

FIG. 6 is a block diagram showing the configuration of a static memory as an example of a conventional general-purpose memory.

In the figure, 1a and 1b are address buffers, 2 is a row decoder, 3 is a column decoder, 4 is a memory cell array, 5 is an input/output control circuit, 6 is a sense amplifier/selector, and 7 is a data input/output buffer. .

In FIG. 6, five upper addresses A5 to A9 of external designated address lines AQ-A9 are stored in an address buffer 1a and specify a row of the memory cell array 4 through a row decoder 2, and lower addresses A□ to A4 are used as addresses. The data is stored in the buffer 1b, and the column of the memory cell array 4 is specified through the column decoder 3, thereby determining the address of the memory cell array 4 to be accessed.

Reading and loading of data via the external data lines (Ilo)o to CIlo)t-1 is controlled by the input/output 1 control circuit 5.

That is, at the time of reading, the data at the specified address in the memory cell array 4 is selected by the sense amplifier/selector B, the read signal is amplified, and the data is sent through the data output buffer 7 to the external data line (Ilo) o~
(Ilo) Output to t-1.

When writing, the external data line (Ilo)
) From t-1, data is written to the selected address of the memory cell array 4 by the sense amplifier/selector 6 via the data output buffer 7.

As mentioned above, conventional general-purpose memory has a bit length (bit length that constitutes data per address).

The word length (corresponding to the number of words when data per address is one word) is fixed, and memories with various bit lengths such as 1, 2, 8, 16, and 52 bits are available. each made. 1 system,
When several types of memories with different bit lengths are required, a wide variety of memories have been developed in order to use memories with different bit lengths and word lengths.

The development of such a wide variety of products leads to an increase in development costs. Therefore, as a specific example of a system that uses multiple types of memory, we will cite a baseband switch in a satellite-mounted switching system, whose configuration is shown in Figure 7. The problems when using different types of conventional memory are explained.

As shown in FIG. 7, the baseband switch includes a multiplex concentrator 82, a demultiplexer 95, a time switch mount 10, a channel controller @11. Subscriber line signaling device 12, communication line common control device 15. It is composed of a central control device 14 and a main storage device 15.

Among these devices, in the time switch device 10,
When a memory that is generally used as a time switch memory and has a capacity of, for example, 32 bits in bit length and 2048 words in length is also used as a time switch control memory, the required bit length of the time inch control memory is lo
g, 2048 = 11 bits is sufficient, so only 132 of the total capacity of one memory is used, and 2'152 of the total capacity is wasted. Similarly, if a memory with the above-mentioned capacity is used as the main memory in the main storage device 15, the central controller 14 has 808
When a 16-pit CPU such as No. 6 is used, there are 16 data lines, so the total capacity of one memory is wasted.

In other words, if we stopped developing multiple types of memory because it would increase costs, and instead used a single type of memory uniformly even when memory with different bit lengths was required, the problem described above would be This can result in a large waste of memory capacity, leading to an increase in costs.

However, developing a memory with moderate bit and word lengths that is radiation-resistant and suitable for use onboard satellites will inevitably lead to increased costs.

[Problem that the invention seeks to solve]

Therefore, in the present invention, when memories with different bit lengths are required, even if a single type of memory is uniformly used, there is no need to waste memory capacity. This is an issue that should be addressed.

Therefore, the present invention is designed to prevent wasted capacity even if one type of memo LSI is used for general systems that require memories with various bit lengths and word lengths. By adding a simple control circuit to a variable bit length memory (that is, one type of memory IJLSI),
The purpose is to provide memory with variable bit length.

[Means and operations for solving the problem] The variable pit length memory according to the present invention is a memory in which data can be written or read at a specified address via an input/output data line. Means for specifying the bit length constituting data, and address conversion means for converting a specified address into an address corresponding to the bit length according to the specified bit length. It is characterized in that it is equipped with a data line switching means for switching to an appropriate data line, and that the bit length constituting the data of one address is variable.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 2 is a row decoder, 3 is a column decoder, 5 is an input/output control circuit, and 16 is a bit length mode designation circuit, where the bit length per address is 8,163 as an example.
! A circuit for selecting and specifying one of the 12 bits, 17 an address conversion circuit, 18 a data storage circuit, and 19 a data line switching circuit.

The bit length mode specification in the circuit 16 can be done by wiring the signal lines MDO and MDI as shown in FIG. 1, or by connecting the signal lines to the data line from the CPU and specifying it programmably. There is a way to do this.

The data of the mode designation data signal line MDO) MD1 is (MI)+, MDo)=(0,0), (0
, 1), (1, 0), the bit length is 8, 16, 3
In this case, the word length is 4 as shown in Figure 2 (a), (b), and (C).
096.

It becomes 2048.1024.

Note that FIG. 2 is an explanatory diagram showing various (five types in this example) address spaces realized within the same memory (one day in FIG. 1) according to the present invention.

Returning to Figure 1, (MDl, MDo) = (0, O)p
(0x1), c1*o), the data on the internal mode control lines MQ, Ml, and M2 from the bit length mode designation circuit 16 becomes (M2
, Ml.

Mo)””Cop op i), (o, 1,0)7(
1, o, o).

In accordance with each bit length mode specified by 5, the address conversion circuit 17 converts the externally specified address lines AQ to
A9 is the block enable line M of the data storage circuit 18
EQ-ME3. and internal designated address gland l5-dr
It is converted into O~Adr 7 .

Block enable aMEo of data storage circuit 18 = M
E3 is connected to each block of the data storage circuit 18 divided into four (indicated by broken lines), and among the block enable lines ME□-ME3, M which becomes "high"
E, - Block connected to ME3 is enabled, 60
-”, the block connected to ME 3 is disabled.

Further, among the internal designation address lines AdrO to Adr7, Adr4 to Adr7 designate the row of the memory cell array of each block in the data storage circuit 18 through the row decoder 2, and AdrO to Adr3 designate the row of the memory cell array of each block in the data storage circuit 18 through the row decoder 2. 3, by specifying the column of each memory cell array, the specified address of each memory cell array is determined,
When reading, data storage circuit block enable a
After the sense amplifier/selector (not shown) belonging to the block enabled by MEo-ME5 reads and amplifies the data at the address, the internal data +\l! i!
It is outputted to the external data lines (Ilo)o to Cl10) 31 via Da-Dsi and the data line switching circuit 19.

When writing, external data MA (Ilo) o~(
Data is transferred from Ilo) 31 through the data line switching circuit 19 and via the internal data line Do-D51 to the designated address of the memory cell array of the block enabled by the data storage circuit block enable lines M E o - M E s. is written.

In addition, in the data line switching circuit 19, internal mode control lines Mo, M, , M from the bit length mode specifying circuit 16
The required switching is performed by the data depending on the bit length designation and the external designated address AOy A1 on 2 (this will be described later).

Read and write control is performed by the input/output control circuit 5.

When performing read control, chip enable line C
E1 is set to high, CEO is set to low, output enable line OE is set to low, write enable line WE is set to high.
As a result, the input/output control circuit 5 sets the internal enable ilE to "no" and the input/output control line R/W to "high" to perform reading.

In addition, when performing read-in control, the chip enable line CE1 should be set to ``high'', the CEO to ``low'', the output enable line OE to ``high'', and the read-in enable 1lWE to ``low''. As a result, the input/output control circuit 5 sets the internal enable line E to "high".

Write by setting the input/output control line R/W to 'low'.

Hereinafter, detailed explanation of each circuit in FIG. 1 will be given.

FIG. 6 is a block diagram showing details of the address translation circuit 17 in FIG. 1. In the same figure, 20a to 20o
are address buffers 21a, respectively.

21b is a demultiplexer that sends signals to data storage circuit enable lines MEo to ME5, and G is a 3-state gate.

When the designated bit length mode is 8-bit mode, the bit length designation circuit 16 selects the address buffer 20a and the (2 to 4) demultiplexer 21a.
is enabled, and A2 to A9 of the external specified address lines AO-A9 pass through the address buffer 20a,
Connected to internal specified address lines Adr O to Adr 7, using the remaining A Op A 1, (2 to 4)
The demultiplexer 21a sets one of the data storage circuit enable lines M E O - M E 3 to 6 high.
so that it becomes

Similarly, when the 16-bit mode is specified, the address buffer 20b and the (1 to 2) demultiplexer 21
b is enabled, and the external specified address line A□-A9
Among them, Ai to A13 are connected to internal designated address lines AdrO to Adr7 through the address buffer 20b, and the remaining AOs are opened (It.

2) By the demultiplexer 21b, when AO is "low", MEO and MEL are set to "1", and when A□ is "0 high", MB2 and MB2 are set to "1" and "1", respectively. In this case, A9 is °don't car
It is e.

When the 52-bit mode is specified, the internal mode signal line M2 pulls the 3-state gate G to enable, so that all MEo to MEs become "high", and the externally specified address #AQ-A9 Among them, AQ-A7 is connected to internal addresses aAdrO to Adr7 through an address buffer 20c. In this case, A8pA9 is a don't care.

FIG. 4 is a block diagram showing details of the data line switching circuit 19 in FIG. 1. In the same figure, 22a to 22c
are data selector/buffer circuits, respectively.

When the 8-pit mode is specified, the data selector/buffer circuits 2 and 2a are enabled, and according to the data on the externally specified address line AOyA1, (AI, AQ
) = (0,0), (0,1), (1,0).

(1, i), internal data lines DQ to D7 .
D13~D15yD16~D23 J D24~D31
is the outsider data line (I/O) o ~ (I/O) sl
Among them, (Ilo)o to (Ilo'')y are connected. In this case, data lines (Ilo)o to (Ilo'')
) 31 becomes high impedance during reading and becomes don'tcare during writing.

When the 16-bit mode is specified, the data selector/buffer circuit 22b is enabled, and if the external designated address line AO is "low", the internal data line Do-
If D15 and AQ are 1 nohei, then DI6 to D51 are
External data a (Ilo) o ~ (Eng. 10) 31-5
In other words, it is connected to (Ilo)o to (Ilo)1s. In this case, data lines (10) 16 to (Ilo) 31
becomes high impedance when reading, and becomes don't care when writing.

When the 32-bit mode is specified, the data selector/buffer circuit 22c is enabled, and the internal data line Do-D31 and the external data line (work 10) o to (Ilo
) 31 is connected.

FIG. 5 is a block diagram showing details of the data storage circuit 18 in FIG. 1. In the figure, 23a to 23d are memory cell arrays, and 24a to 24d are sense amplifiers/selectors, respectively.

A row of each memory cell array 24a to 24d is designated by the row decoder 2 according to internal designated address lines Adr4 to Adr7, and internal designated address lines AdrO to Adr3 are designated by the row decoder 2.
Accordingly, the column decoder 6 specifies the column of each memory cell array 24a to 24d, and thereby the specified memory cell address is determined.

At the time of reading, the sense amplifiers/selectors 24a to 24
d, data storage circuit enable line MEO-MB2
Sense amplifier corresponding to "high" among
Only the selector amplifies the data signal from the address cell and outputs it onto the internal data line.

At the time of writing, similarly, only the sense amplifier/selector corresponding to the data storage circuit enable line MEo=ME5 which is "high" writes data from the internal data line to the memory cell at the corresponding address.

〔Effect of the invention〕

As explained above, for example, a baseband switch in a satellite-mounted exchange requires a number of memories with different required bit lengths depending on each functional block, but if radiation resistance is taken into consideration, -8 degrees of memory is required. 5, which addresses this problem, is advantageous in terms of cost and reliability.

The present invention is capable of satisfying these requirements, and the number of pits that constitute data per address can be varied as necessary, making it possible to use memory capacity efficiently. There is also the advantage that the Mk can be reduced as a result.

Furthermore, the variable bit length memory according to the present invention is effective not only for the above baseband switch but also for general systems.Also, although static memory was taken up in the above embodiment, the variable bit length memory according to the present invention is also effective for use in dynamic memory. It goes without saying that the invention is effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing various address spaces realized within the same memory according to the present invention, and FIG. 6 is an address conversion circuit in FIG. 1. A block diagram showing the details of 17, Fig. 4 is the 1st
FIG. 5 is a block diagram showing details of the data line switching circuit 19 in FIG. 1, FIG. 5 is a block diagram showing details of the data storage circuit 18 in FIG. 1, and FIG. 6 shows a static memory as an example of a conventional general-purpose memory. FIG. 7 is a block diagram showing the configuration of a baseband switch as a specific example of a system using a multi-component memory. Code explanation AQ-A9... External designated address line, (Ilo
). ~(Ilo)t-1...External data line, CE
l, OE2...Chip enable line, OE...
...Output enable green, WE...Input enable line, MDo, MDl...Mode designation data line, AdrO to Adr7...Internal address line, Do""I) 51...Internal data line, E.
...--Internal enable line, R/W...Input/output control line, MO-M2 ''--Internal mode control line, ME
o-MB2...Data storage circuit block enable line, G°°゛...6 state gates, 1a, 1b
・・・-Address number (tsu, nua, 2...row decoder, 3...column encoder, 4...memory cell array, 5...input Output control circuit, 6.
...Sense amplifier/selector, 7...Data input/output buffer, 8...Multiple east line device, 9
... Separation device, 10 ... Time switch device, 11 ... Call path control device, 12 ...
...Subscriber line signaling device, 15...Communication path system common control device, 14...Central control device, 15...
... Main memory device, 16 ... Bit length mode designation circuit, 17 ... Address conversion circuit, 18 ...
...Data storage circuit, 19...Data line switching circuit, 20a-20c...Address buffer, 21a, 21b...Demultiplexer, 2
2a to 22c...Data selector/buffer circuit, 23a to 23d...Memory cell array, 2
4a-24d...Sense Amplifier/Selector Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Figure 2

Claims (1)

[Claims] 1) In a memory in which data can be written or read via an input/output data line at a specified address, a means for specifying the bit length constituting data per address, and a method according to the specified bit length. ,
an address conversion means for converting a specified address into an address corresponding to the specified address, and according to the bit length also specified,
A variable bit length memory comprising: data line switching means for switching an input/output data line to a data line corresponding to the input/output data line, and wherein the bit length constituting data per address is made variable.