JPS6159533A - Storage device access control system - Google Patents

Abstract

PURPOSE:To reduce remarkably an access waiting time at each flow by using the flow identification number of a storage device access request so as to select plural registers and access a register. CONSTITUTION:The storage address of access request given from a flow having an instruction control section is set to an address register 10 and the access to a buffer 11 is tried by using an address converted into a real storage address by an address converting circuit 16. A flow identification number generated by a counter circuit 20 is set to registers 22-1-22-3 at the same time. The identification number of the register 22 is shifted sequentially to the registers 22-2-22-m. The register 23-1 consists of three-stage constitution with registers 23-2 and 23-3, each stage corresponds to pipeline stages A, T, B of an instruction control section and shifted as each flow identification number is progressed. This identification number is used for the selection control of one register to be outputted from a data register group 24 and an exception register group 25, and the selected output is transmitted to an E stage of the pipelines where it is processed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to instruction execution control of an information processing device, and particularly to an improved control method for storage device access in instruction execution using a pipeline control method.

A pipeline control method for executing instructions in an information processing device is well known as a control method for simultaneously executing a plurality of instructions in parallel.

In a pipeline control method, each of multiple stages connected in series to form a pipeline generally performs a different function that is part of instruction execution, and by passing through such stages sequentially, the required instruction execution is completed.

At each stage, partial executions for different instructions are generally executed in parallel, so the entire pipeline can logically be thought of as having multiple processing flows proceeding in parallel, each of which (pipe line) flow.

Since the stages of the pipeline are serial, if a certain stage takes a long time to execute, the progress of subsequent processing is suppressed by the stage that takes a long time to execute.

[Conventional technology]

Therefore, when designing a pipeline, we try to avoid a huge difference in the execution time of each stage, but because the required data is not in the so-called Hesopha, which is made up of high-speed memory, the flow of reading data from the main memory is Alternatively, a flow that is in a stage subsequent to a stage of a flow that requires a particularly long calculation time (eg, a division instruction) may have excessive waiting time.

FIG. 2 fat is a block diagram showing the configuration of a storage access control unit that processes storage access requests issued from the pipeline flow of the instruction control unit.

The storage address in the storage access request is set in the address register 10, the address is converted by the address conversion circuit I6, and access to the sofa 11 is first attempted.

At the same time, the address is also input manually to the access exception checking unit 12, and for example, the memory protection key set to the address,
The validity of the access execution is checked by comparing it with the access key granted to the program being executed.
The result is set in the exception information register 13.

If data at the requested address is stored in the buffer 11, the data is read out and stored in the data register 14.
The contents of the data register 14 and exception information register 13 are transferred to the instruction control unit and used for instruction execution. However, if there is information indicating an illegal access in the exception information register 13, normally, for example, an interrupt is generated to interrupt instruction execution.

If there is no data for the requested address in the buffer 11,
After sending the address of the address register 10 to the main memory 15 to start an access operation and storing the read data in the buffer 11,
1, the processing of the access request is completed. .

In this way, when accessing the main storage device 15, it takes a considerably longer access time than when the access ends in the buffer 11, but since the requesting flow cannot proceed unless data is obtained, it is difficult for the subsequent flow to proceed. Progress also stops and a memory access wait occurs.

FIG. 2(b) is a diagram showing the timing of such a waiting state.

The symbols shown in the instruction control section in the figure each represent the function of one stage of the pipeline, where D is instruction decoding, A is operand address calculation, T is address conversion, B is continuous operand data from the buffer, and E is the calculation execution, W
indicates that the processing result data is at each stage of aging (however, at T and B, an access request is sent to the storage access control unit as described below, and the control unit executes address conversion and buffer access. ).

In the diagram, the symbol strings lined up horizontally represent one flow (each is
) indicates the stage it occupies as the process progresses,
Therefore, consecutive symbols indicating the same stage indicate that the stage is stopped at the same stage, and the processing time of that stage is long, or the stage is waiting because the previous stage is not available.

Each vertical column represents a stage occupied by a different flow that is in the pipeline at the same time.

Also, in the pipeline of the storage access control unit in the figure, symbol 1] indicates selection of a storage access request issued from the instruction control unit, T indicates address translation, B indicates buffer readout, and
~■ correspond to the flows with the same number in the instruction control section.

If the data is in the buffer, the access is completed by P-T-B processing, but if there is no target data in the buffer as a result of this processing, for example, access to the main memory is performed (Fig. (partially starting from time l of
The access is completed at .

During this time, the access requests of other flows are made to wait, flow (1) remains at the T stage, flow (2) remains at the A stage, and at time 3, the access request of flow (2) is accepted by the storage access control unit.

In this way, if the access requests of flow ■ and flow ■ also require access to the main memory, the access request of flow ■ advances to the A stage at time 4 and is started, but it is not completed. It is delayed until time 5.

[Problem that the invention seeks to solve]

As mentioned above, conventionally, main memory access requests for each flow are processed serially in time, so if access requests are made consecutively, the waiting time becomes extremely large and the effective instruction processing capacity is reduced. There was a problem.

[Means for solving problems]

The above-mentioned problem is that in an information processing device that executes instructions using a pipeline control method, there is a means for setting a flow identification number for each flow flowing through a pipeline, and a means for holding data read from a storage device and storage device access exception information. This problem is solved by the storage device access control method of the present invention, which has a plurality of register means and is configured to select and access the register according to the flow identification number of the storage device access request source.

[Effect]

Multiple sets of registers are provided to hold read data from the storage device and access exception information corresponding to each flow flowing through the pipeline, and each register has a flow identification number assigned to each flow. so that they can be accessed separately.

With this configuration, multiple access requests can be processed in parallel and data can be processed in advance, asynchronously with the progress of the instruction control unit's pipeline, until parallel access is possible due to the functionality of the storage device. Since it is possible to prevent inconsistencies from occurring even if the information is acquired, it is possible to significantly reduce the access waiting time for each flow.

〔Example〕

FIG. 1 (al is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 1 (bl is a control timing diagram thereof).

The storage address of an access request issued from a certain flow of the instruction control unit is set in the address register 10 in the same manner as described above, and access to the buffer 11 is performed in 8 types according to the address converted to a real storage address by the address conversion circuit 16. will be carried out.

At the same time, the flow identification number generated by the counter circuit 20 is set in the register 22-1 and the register 23-1.

The counter circuit 20 is, for example, a counting circuit that repeatedly counts at a period equal to the maximum number of flows in which memory accesses are simultaneously proceeding.

The flow identification number in register 22-1 is shifted to register 22-2 in the next cycle (T cycle described above).

The register 22-2 is further connected in series to the registers 22-3 to 22-m and 22-1 to form a circular shift register. The length of this shift register is shifted every cycle so that it completes one cycle in the access time of the main storage device 15.

If there is target data in the buffer 11, it is read out in the same manner as described above and set in the register selected by the flow identification number of register 22-2 in the data register group 24. At the same time, exception information is set in the register selected by the flow identification number of register 22-2 in the exception information register group 25.

The register 23-1 and the registers 23-2 and 23-3 constitute, for example, a three-stage shift register, each stage corresponding to the A, T, and B stages of the pipeline stage of the instruction control section. It is assumed that the flow identification number is shifted as the flow identification number progresses.

The flow identification number shifted to the register 23-3 in this way is stored in the data register group 24 and the exception register group 25.
The selected output is used for control to select each register to output from
It is sent to the stage and processed in the same way as before.

In FIG. 1(b), the timing of the above operations will be explained using the same symbols as in FIG. 2(b).

In the same way as above, the access requests issued from flows ■ to ■ are accepted and activated to access the main storage device 15 in each cycle, so the access operations of the main storage device proceed in parallel, and the access requests issued from flows ■、■ are waiting for access,
significantly shortened.

In this embodiment, since the configuration is such that up to three requests are processed in parallel, the acceptance of access for flow (2) is delayed until the access for flow (0) is completed.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the stagnation of the pipeline flow due to waiting for access to the main memory during instruction execution using the pipeline control method is significantly improved, thereby improving the performance of the processing device. It has significant industrial effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration and timing diagram of a storage access control unit according to an embodiment of the present invention, and FIG. 2 is a conventional configuration and timing diagram. In the figure, 10 is an address register, 11 is a buffer, 12 is an access exception checker, 13 is an exception information register, 14 is a data register, 15
is the main memory, 20 is a counter circuit, 22-1~
22-m, 23-1 to 23-3 are registers, 24 is a data register group, and 25 is an exception register group.

Claims (1)

[Claims] An information processing device that executes instructions using a pipeline control method, which includes means for setting a flow identification number for each flow flowing through a pipeline, and a plurality of register means for holding data read from a storage device and storage device access exception information. A storage device access control system characterized in that the register is selected and accessed based on a flow identification number of a storage device access request source.