JPS6158058B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input signal identification and regeneration circuit used in a PCM repeater or the like.

A PCM repeater instantly identifies whether the input signal is "+", "-", or "0" at a time determined by a clock signal, and as a result,
If identified as “+” or “-”, “+”
Alternatively, an RZ (return to zero) waveform pulse of "-" is sent out, and if it is identified as "0", no pulse is sent out.

A conventional circuit that performs such identification and reproduction is as follows.
NTC'77 (National Telecommunications Conference) was held in Los Angeles, USA from December 5th to 7th, 1977.
44:1-1 to 44:1-3 of the Conference Record of the
LOW POWER REGENERATIVE REREATER
FOR THE CARRIER SYSTEM
The pulse regeneration circuit shown in FIG. 4 of ``The Carrier System'' is known.

This regeneration circuit consists of a circuit 1 that identifies the presence or absence of an input signal supplied to the terminal E _O and a circuit (gate circuits 3 and 4) that identifies the presence or absence of an input signal at the falling edge of the clock signal supplied to the clock terminal. and a capacitor) and a flip-flop circuit consisting of gate circuits 6 and 7; and a second regeneration circuit having the same configuration as this first regeneration circuit. Because the circuit configuration is complex and all circuits are always active,
It has the disadvantage of high power consumption. Furthermore, since such a regeneration circuit uses a capacitor, it has the disadvantage that it is difficult to form it into a semiconductor integrated circuit (monolithic IC).

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide an identification reproducing circuit with a simple circuit configuration and low power consumption.

The identification and reproduction circuit of the present invention has a first input terminal that receives first ternary data that is in phase with the input data obtained from the ternary input data, and a first input terminal that receives the first ternary data that is in phase with the input data obtained from the input data. a second input terminal for receiving two ternary data; a third input terminal for receiving a clock signal generated from the input data; and first and second timing signals that are in phase and opposite to the clock signal, respectively. means for creating a 3-value data, an identification means for comparing the first and second ternary data with a predetermined value in response to the first timing signal and outputting the respective comparison results; Detection means for detecting whether or not one of the two comparison results of the identification means is output in response to a timing signal; and means for holding the output comparison result in response to the output of the detection means. It is characterized by being composed of.

Next, the present invention will be explained in detail with reference to the drawings.

FIGS. 2 and 3 are a block diagram and a waveform diagram showing one embodiment of the present invention.

The identification reproducing circuit of the present invention is composed of an identification circuit 5, a gate circuit 6, and flip-flops 7 and 8. Input terminals 9 and 10 are supplied with positive phase and negative phase data (FIG. 2 a and b) obtained from the transmitted input data by an equalizing amplifier (not shown). Further, a clock signal (FIG. 2c) generated by a timing circuit (not shown) based on input data is applied to the terminal 17. The gate circuit 6 generates a positive phase timing signal (FIG. 2c) and a negative phase timing signal (FIG. 2g) from the clock applied to the terminal 17. The identification circuit 5 compares the positive phase and negative phase data with a threshold value V _R in response to the positive phase timing signal, and when the positive phase or negative phase data is greater than the threshold value _VR , a positive identification signal (FIG. 2 d) or A negative identification signal (Fig. 2e) is output. Further, this identification circuit 5 outputs a zero identification signal when both the positive phase and negative phase data are smaller than the threshold value V _R (FIG. 2f). When the zero identification signal is "0" at the rising edge of the negative phase timing signal, the flip-flop 8 outputs "1" as a detection signal during the period of "1" of the negative phase timing (FIG. 2b). On the other hand, the flip-flop 7 converts the positive identification signal and negative identification signal at the rising edge of the detection signal into a positive reproduction signal (FIG. 2i) and a negative reproduction signal (second
As shown in Figure j), during the period when the detection signal is "1", the terminal 18
and output to 19. These positive and negative reproduced signals are combined by the transformer shown in FIG. 4 of the above-mentioned document and then supplied to the transmission line again or supplied to the terminal equipment for data demodulation.

FIG. 3 is a specific circuit diagram of the present invention. The identification circuit 5 is made up of transistors Q1, Q2 and Q3, and the gate circuit 6 is made up of transistors Q4 and Q5 and a current source I. The flip-flop 8 is composed of transistors Q6 and Q7, a resistor R1, and a level shift circuit N.
Flip-flop 7 includes transistors T8, Q9,
It consists of Q10 and Q11, and resistors R2, R3, R4 and R5. Terminal 20 is a reference voltage input terminal that determines whether the input signals of terminals 9 and 10 are "1" or "0". In Figure 3, the current source I
Since it is a single device, it operates with very low power.

As described above, in the present invention, since the circuit can be configured in one system, the circuit can be simplified and power consumption can be reduced.

[Brief explanation of the drawing]

1 and 2 a to 2 j are block diagrams and waveform diagrams showing one embodiment of the present invention, and FIG. 3 is a diagram showing a specific circuit of the present invention. In FIG. 1 and FIG. 3, Q1 to Q11...
...Transistor, N...Level shift circuit, R1
~R5...Resistor, I...Current source, 6...Gate circuit, 5...Identification circuit, 7,8...Flip-flop circuit, 9,10...Signal input terminal, 17...Clock input terminal, 18, 19...Output terminal.

Claims (1)

[Claims] 1. A first input terminal that receives first ternary data that is in phase with the input data obtained from the ternary input data, and receives second ternary data that is in opposite phase to the input data that is obtained from the input data. a second input terminal, a third input terminal for receiving a clock signal generated from the input data, means for generating first and second timing signals respectively in phase and opposite phase to the clock signal; said first and second three in response to a first timing signal.
first and second comparison outputs that compare the value data with a predetermined value and indicate that the first and second ternary data are larger than the predetermined value; an identification means for generating a third comparison output indicating that both are smaller than the predetermined value; and a third comparison output in response to the second timing signal.
means for generating an indication pulse indicating that a signal larger than the predetermined value is present in the first and second ternary data of the identification means from the comparison output of the apparatus; and means for holding comparison results.