JPS6157098A - メモリ制御方式 - Google Patents

メモリ制御方式

Info

Publication number
JPS6157098A
JPS6157098A JP59178473A JP17847384A JPS6157098A JP S6157098 A JPS6157098 A JP S6157098A JP 59178473 A JP59178473 A JP 59178473A JP 17847384 A JP17847384 A JP 17847384A JP S6157098 A JPS6157098 A JP S6157098A
Authority
JP
Japan
Prior art keywords
signal
address
becomes
circuit
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59178473A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0370878B2 (enrdf_load_stackoverflow
Inventor
Giichi Shimizu
清水　儀一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59178473A priority Critical patent/JPS6157098A/ja
Publication of JPS6157098A publication Critical patent/JPS6157098A/ja
Publication of JPH0370878B2 publication Critical patent/JPH0370878B2/ja
Granted legal-status Critical Current

Links

JP59178473A 1984-08-29 1984-08-29 メモリ制御方式 Granted JPS6157098A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59178473A JPS6157098A (ja) 1984-08-29 1984-08-29 メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59178473A JPS6157098A (ja) 1984-08-29 1984-08-29 メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS6157098A true JPS6157098A (ja) 1986-03-22
JPH0370878B2 JPH0370878B2 (enrdf_load_stackoverflow) 1991-11-11

Family

ID=16049114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59178473A Granted JPS6157098A (ja) 1984-08-29 1984-08-29 メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS6157098A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0166697U (enrdf_load_stackoverflow) * 1987-10-23 1989-04-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0166697U (enrdf_load_stackoverflow) * 1987-10-23 1989-04-28

Also Published As

Publication number Publication date
JPH0370878B2 (enrdf_load_stackoverflow) 1991-11-11

Similar Documents

Publication Publication Date Title
JPS58184668A (ja) メモリの書込み制御方式
JP2882426B2 (ja) アドレス発生装置
JPS6157098A (ja) メモリ制御方式
JPH04255043A (ja) 改良された外部メモリアクセス制御システム
JP2833349B2 (ja) ダイナミックメモリ制御方式
US20060047866A1 (en) Computer system having direct memory access controller
JP2730240B2 (ja) マイクロコンピュータ・システム
JP3266610B2 (ja) Ｄｍａ転送方式
JP2575025B2 (ja) インサ−キット・エミュレ−タ
JPH07114496A (ja) 共有メモリ制御回路
JPS63198110A (ja) 電子機器の動作速度制御方式
JPH03160690A (ja) メモリシステム
JP2909126B2 (ja) メモリ制御装置
JP2522571B2 (ja) 電子機器のデ―タ転送装置
JPH03201036A (ja) マイクロコンピュータ
JP2625573B2 (ja) ダイレクトメモリアクセス制御装置
JP3131918B2 (ja) メモリ装置
KR100302586B1 (ko) 피씨 카드 에이티에이 카드의 파워다운 및 슬립모드 전환 방법
JPH0138692Y2 (enrdf_load_stackoverflow)
JPH052415A (ja) 数値制御装置
JPH081631B2 (ja) Ｄｍａ制御装置
JPH0142017B2 (enrdf_load_stackoverflow)
JPH0520868A (ja) メモリアクセス方法
JPH03211634A (ja) データトレース方式
JPH052553A (ja) メモリ制御システム