JPS6156622B2 - - Google Patents
Info
- Publication number
- JPS6156622B2 JPS6156622B2 JP8089078A JP8089078A JPS6156622B2 JP S6156622 B2 JPS6156622 B2 JP S6156622B2 JP 8089078 A JP8089078 A JP 8089078A JP 8089078 A JP8089078 A JP 8089078A JP S6156622 B2 JPS6156622 B2 JP S6156622B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- guide
- cutting
- frame
- envelope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005520 cutting process Methods 0.000 claims description 32
- 239000011521 glass Substances 0.000 description 8
- 238000000465 moulding Methods 0.000 description 6
- 235000014676 Phragmites communis Nutrition 0.000 description 4
- 238000005452 bending Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 244000273256 Phragmites communis Species 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8089078A JPS558065A (en) | 1978-07-05 | 1978-07-05 | Lead wire cutting moulding machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8089078A JPS558065A (en) | 1978-07-05 | 1978-07-05 | Lead wire cutting moulding machine |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS558065A JPS558065A (en) | 1980-01-21 |
| JPS6156622B2 true JPS6156622B2 (enrdf_load_html_response) | 1986-12-03 |
Family
ID=13730939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8089078A Granted JPS558065A (en) | 1978-07-05 | 1978-07-05 | Lead wire cutting moulding machine |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS558065A (enrdf_load_html_response) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02109601U (enrdf_load_html_response) * | 1989-02-17 | 1990-09-03 |
-
1978
- 1978-07-05 JP JP8089078A patent/JPS558065A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02109601U (enrdf_load_html_response) * | 1989-02-17 | 1990-09-03 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS558065A (en) | 1980-01-21 |
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