JPS6156619B2 - - Google Patents
Info
- Publication number
- JPS6156619B2 JPS6156619B2 JP53067967A JP6796778A JPS6156619B2 JP S6156619 B2 JPS6156619 B2 JP S6156619B2 JP 53067967 A JP53067967 A JP 53067967A JP 6796778 A JP6796778 A JP 6796778A JP S6156619 B2 JPS6156619 B2 JP S6156619B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- lead
- mounting
- mounting portion
- mounting part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 238000009751 slip forming Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48253—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a potential ring of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は伸積回路装置に関し、特に搭載部の改
良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an expansion circuit device, and more particularly to an improvement in a mounting section.
一般に集積回路装置は、半導体素子とこの半導
体を収納する容器とから成り、この容器は容器内
部より容器外部に引出されるリード線と半導体素
子を取付ける搭載部を備えたフレームと、蓋部材
とからなつている。 Generally, an integrated circuit device consists of a semiconductor element and a container that houses the semiconductor. It's summery.
このような集積回路装置の搭載部は、集積回路
素子の搭載を保持する保持リードを有し、このリ
ード部は集積回路素子の装着のみに用いていた。
また搭載部に接続している外部導出リードは、集
積回路素子の最低電位を導出していた。 The mounting section of such an integrated circuit device has a holding lead for holding the integrated circuit element mounted, and this lead section is used only for mounting the integrated circuit element.
Furthermore, the external lead connected to the mounting section derives the lowest potential of the integrated circuit element.
第１図および第２図は、従来の集積回路装置を
示し、これらの図面において、銅またはコバルト
などで作られているフレーム１の表面には、金属
化層により集積回路素子の搭載部２が形成され、
この搭載部２には集積回路素子３が取り付けられ
ている。前記搭載部２の周囲には、先端が集まる
ように外部導出リード４が配線されているととも
に、搭載部２には保持リード５が連設されてい
て、６はモールド樹脂部ラインを示す。 1 and 2 show conventional integrated circuit devices, in which the surface of a frame 1 made of copper or cobalt or the like has a mounting part 2 for an integrated circuit element by means of a metallized layer. formed,
An integrated circuit element 3 is attached to this mounting portion 2 . External lead-out leads 4 are wired around the mounting portion 2 so that their tips are gathered together, and holding leads 5 are connected to the mounting portion 2, and 6 indicates a line of the molded resin portion.
このような従来の集積回路装置によれば、集積
回路素子３の最低電位をワイヤ結線により外部導
出リード４のいずれにも自由に導出できるよう
に、搭載部２は外部導出リード４のいずれとも接
続していない。 According to such a conventional integrated circuit device, the mounting portion 2 is connected to any of the external lead-out leads 4 so that the lowest potential of the integrated circuit element 3 can be freely led to any of the external lead-out leads 4 by wire connection. I haven't.
このため、集積回路素子３からの搭載部２への
漏れ電流が、集積回路素子３に帰還し集積回路素
子の電気的特性に悪影響を及ぼす欠点があつた。
また、このような欠点を改善するために集積回路
装置が専門になり多種になつてしまう。 Therefore, the leakage current from the integrated circuit element 3 to the mounting portion 2 returns to the integrated circuit element 3, resulting in a disadvantage that it adversely affects the electrical characteristics of the integrated circuit element.
Moreover, in order to improve these drawbacks, integrated circuit devices become specialized and become diverse.
また第３図および第４図は、従来における他の
実施例を示し、これらの図面において、前記第１
図および第２図と同一部分は同一符号で示しその
説明は省略する。これらの図面において、３ａは
集積回路素子３の最低電位電極で、この最低電位
電極３ａと搭載部２に接続している第２の外部導
出リード７をワイヤ結線していた。 Further, FIGS. 3 and 4 show other conventional embodiments, and in these drawings, the first
Components that are the same as those in the figures and FIG. In these drawings, 3a is the lowest potential electrode of the integrated circuit element 3, and the lowest potential electrode 3a and the second external lead 7 connected to the mounting portion 2 are wire-connected.
このような従来の集積回路装置によれば、集積
回路素子の最低電位を最低電位電極３ａと第２の
外部導出リード７のワイヤ結線で導出していたの
で、最低電位電極３ａの位置がワイヤ結線上制限
された位置となり、集積回路素子設計上大きな制
限となる欠点があつた。 According to such a conventional integrated circuit device, the lowest potential of the integrated circuit element is derived by the wire connection between the lowest potential electrode 3a and the second external lead 7, so that the position of the lowest potential electrode 3a is determined by the wire connection. This has the disadvantage that the position is restricted, and this poses a major restriction on the design of integrated circuit elements.
本発明の目的は、搭載部に外周部を形成して上
記従来の問題点を解決した集積回路装置を提供す
ることにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device in which the above-mentioned conventional problems are solved by forming an outer peripheral part in the mounting part.
本発明は、フレーム上に形成されている集積回
路素子の搭載部と、この搭載部の周囲に配線され
ている外部導出部材と、前記搭載部に連設してい
る保持部材を有する集積回路装置において、前記
搭載部に外周部が連続して形成されていることを
特徴とする集積回路装置を提供することにある。 The present invention provides an integrated circuit device having a mounting part for an integrated circuit element formed on a frame, an external lead-out member wired around the mounting part, and a holding member connected to the mounting part. An object of the present invention is to provide an integrated circuit device characterized in that an outer peripheral portion is continuously formed on the mounting portion.
次に本発明の実施例について図面を参照して説
明する。 Next, embodiments of the present invention will be described with reference to the drawings.
まず、前記第１図および第２図に示した集積回
路装置の問題点を解決するための実施例を第３図
ないし第９図により説明する。 First, an embodiment for solving the problems of the integrated circuit device shown in FIGS. 1 and 2 will be described with reference to FIGS. 3 to 9.
第５図は第１実施例を示し、第５図において、
アルミナまたはベリリアなどのセラミツクで作ら
れているフレーム１１の表面には、金属化層によ
り搭載部１２が形成され、この搭載部１２には集
積回路素子１３が取り付けられている。前記搭載
部１２の周囲には、先端が集まるように外部導出
リード１４が配線されているとともに、搭載部１
２には保持リード１５が連設されている。前記搭
載部１２の外周には、搭載部１２および保持リー
ド１５に接続している外周部１７を設けている。 FIG. 5 shows the first embodiment, and in FIG.
On the surface of the frame 11, made of ceramic such as alumina or beryllia, a mount 12 is formed by a metallized layer, to which an integrated circuit element 13 is attached. External leads 14 are wired around the mounting portion 12 so that their tips are gathered together, and the mounting portion 1
2 is connected with a holding lead 15. An outer peripheral portion 17 is provided on the outer periphery of the mounting portion 12 and is connected to the mounting portion 12 and the holding lead 15 .
上記構成の本発明に係る第１実施例の集積回路
装置においては、搭載部１２および保持リード１
５に接続している外周部１７が該搭載部１２の外
周に設けられているので、搭載部１２への漏れ電
流は外周部１７と保持リード１５を経てバイパス
される。このため、従来のように搭載部１２への
漏れ電流が集積回路素子１３に帰還することがな
い。 In the integrated circuit device of the first embodiment according to the present invention having the above configuration, the mounting portion 12 and the holding lead 1
Since the outer peripheral part 17 connected to the holding lead 15 is provided on the outer periphery of the mounting part 12, leakage current to the mounting part 12 is bypassed through the outer peripheral part 17 and the holding lead 15. Therefore, the leakage current to the mounting portion 12 does not return to the integrated circuit element 13 as in the conventional case.
第６図ないし第９図は第２実施例ないし第５実
施例を示している。これらの図面において、第３
図に示した第１実施例と同一部分は同一符号で示
しその説明は省略する。これらの第６図ないし第
９図において、搭載部１２の外周には、搭載部１
２および保持リード１５に接続するように外周部
１８〜２１がそれぞれ接続されている。 6 to 9 show second to fifth embodiments. In these drawings, the third
The same parts as in the first embodiment shown in the drawings are denoted by the same reference numerals, and the explanation thereof will be omitted. In these FIGS. 6 to 9, the outer periphery of the mounting portion 12 has the mounting portion 1
2 and the holding lead 15, the outer peripheral portions 18 to 21 are connected to each other.
上記構成の本発明に係る第２実施例ないし第５
実施例においても、搭載部１２および保持リード
１５に接続している外周部１８〜２１が該搭載部
１２の外周に設けられているので、前記第１実施
例と同様な機能および効果を有する。 Second to fifth embodiments according to the present invention having the above configurations
In this embodiment as well, since the outer peripheral parts 18 to 21 connected to the mounting part 12 and the holding lead 15 are provided on the outer periphery of the mounting part 12, the same functions and effects as in the first embodiment are obtained.
次に前記第３図および第４図に示した集積回路
装置の問題点を解決するための実施例を第１０図
ないし第１４図により説明する。 Next, an embodiment for solving the problems of the integrated circuit device shown in FIGS. 3 and 4 will be described with reference to FIGS. 10 to 14.
第１０図は第１実施例を示し、前記第５図ない
し第９図と同一部分は同一符号で示しその説明は
省略する。第１０図において、搭載部１２の周囲
には、先端が集まるように第１の外部導出リード
１４が配線されているとともに、搭載部１２には
保持リード１５が連設されている。前記搭載部１
２の近傍には、搭載部１２に接続している第２の
外部導出リード２７が配線されている。このよう
な第２の外部導出リード２７は、保持リード１５
に接続ししかも搭載部１２の外周に設けられてい
る外周部２８にも接続している。 FIG. 10 shows a first embodiment, and the same parts as those in FIGS. 5 to 9 are designated by the same reference numerals and the explanation thereof will be omitted. In FIG. 10, first external leads 14 are wired around the mounting part 12 so that their tips are gathered together, and a holding lead 15 is connected to the mounting part 12. Said mounting section 1
A second external lead 27 connected to the mounting portion 12 is wired near the mounting portion 2 . Such a second external lead-out lead 27 is connected to the holding lead 15.
In addition, it is also connected to an outer peripheral part 28 provided on the outer periphery of the mounting part 12.
上記構成の本発明に係る第１実施例の集積回路
装置においては、搭載部１２に接続している第２
の外部導出リード２７は、搭載部１２の外周に設
けられている外周部２８に接続しているので、集
積回路素子１３の最低電位電極１３ａを搭載部１
２のいかなる位置に配置しても搭載部に接続した
第２の外部導出リード２７に支障なくワイヤ結線
することができる。 In the integrated circuit device of the first embodiment of the present invention having the above configuration, the second
The external lead-out lead 27 is connected to the outer peripheral part 28 provided on the outer periphery of the mounting part 12, so that the lowest potential electrode 13a of the integrated circuit element 13 is connected to the mounting part 1.
2, the wire can be connected to the second external lead 27 connected to the mounting portion without any problem.
第１１図ないし第１４図は第２実施例ないし第
５実施例を示している。これらの図面において、
第１０図に示した第１実施例と同一部分は同一符
号で示しその説明は省略する。これらの第１１図
ないし第１４図において、搭載部１２に接続して
いる第２の外部導出リード２９ないし３２は、保
持リード１５に接続ししかも搭載部１２の外周に
設けられている外周部３３〜３６にそれぞれ接続
している。 11 to 14 show second to fifth embodiments. In these drawings,
The same parts as in the first embodiment shown in FIG. 10 are denoted by the same reference numerals, and the explanation thereof will be omitted. 11 to 14, the second external leads 29 to 32 connected to the mounting portion 12 are connected to the holding lead 15 and are connected to the outer peripheral portion 33 provided on the outer periphery of the mounting portion 12. ~36, respectively.
上記構成の本発明に係る第２実施例ないし第５
実施例においても、搭載部１２に接続している第
２の外部導出リード２９〜３２が、外周部３３〜
３６にそれぞれ接続しているので、前記第１実施
例と同様な機能および効果を有する。 Second to fifth embodiments according to the present invention having the above configurations
In the embodiment as well, the second external leads 29 to 32 connected to the mounting portion 12 are connected to the outer peripheral portions 33 to 32.
36, the same functions and effects as in the first embodiment are obtained.
本発明は以上説明したように外周部が搭載部と
連続して形成されているので、装置を簡易化しな
がら電気的特性を良好に保持ししかも搭載部の設
計上の制限を緩和することができるとともに、最
低電位の自由な導出、設計における自由度の増加
およびパツケージの熱放熱の向上を図ることがで
きるなどの効果を有する。 As explained above, in the present invention, since the outer peripheral part is formed continuously with the mounting part, it is possible to simplify the device, maintain good electrical characteristics, and alleviate design restrictions of the mounting part. At the same time, it has the following effects: the lowest potential can be freely derived, the degree of freedom in design can be increased, and the heat dissipation of the package can be improved.
第１図ないし第４図は従来の集積回路装置の平
面図、第５図ないし第１４図は本発明に係る集積
回路装置の実施例における概略を示す平面図であ
る。
１１……フレーム、１２……搭載部、１３……
集積回路素子、１３ａ……最低電位電極、１４…
…外部導出リード、１５……保持リード、１７〜
２１，２８，３３〜３６……外周部、２７，２９
〜３２……第２の外部導出リード。
1 to 4 are plan views of conventional integrated circuit devices, and FIGS. 5 to 14 are plan views schematically showing embodiments of the integrated circuit device according to the present invention. 11...Frame, 12...Mounting section, 13...
Integrated circuit element, 13a... lowest potential electrode, 14...
... External lead-out lead, 15 ... Holding lead, 17 ~
21, 28, 33-36...Outer periphery, 27, 29
~32...Second external lead.
Claims (1)
搭載部と、この搭載部の周囲に配線されている外
部導出部材と、前記搭載部に連設している保持部
材を有する集積回路装置において、前記搭載部に
外周部が連続して形成されていることを特徴とす
る集積回路装置。1. In an integrated circuit device having a mounting part for an integrated circuit element formed on a frame, an external lead-out member wired around the mounting part, and a holding member connected to the mounting part, An integrated circuit device characterized in that an outer peripheral portion is continuously formed in a mounting portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6796778A JPS54158863A (en) | 1978-06-05 | 1978-06-05 | Integrated-circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6796778A JPS54158863A (en) | 1978-06-05 | 1978-06-05 | Integrated-circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54158863A JPS54158863A (en) | 1979-12-15 |
| JPS6156619B2 true JPS6156619B2 (en) | 1986-12-03 |
Family
ID=13360244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6796778A Granted JPS54158863A (en) | 1978-06-05 | 1978-06-05 | Integrated-circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54158863A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4663650A (en) * | 1984-05-02 | 1987-05-05 | Gte Products Corporation | Packaged integrated circuit chip |
-
1978
- 1978-06-05 JP JP6796778A patent/JPS54158863A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54158863A (en) | 1979-12-15 |
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