JPS6154556A - Inter-memory data transfer system - Google Patents

Abstract

PURPOSE:To prevent the collision of data transferred and to eliminate the waiting state for transmission/reception, by providing a buffer memory between memories in each data transfer direction together with an interruption port which functions to inform a request for transfer of data. CONSTITUTION:When a microprocessor (CPU)101 transfers data stored in a memory 103 to a memory 104, the CPU101 sends the desired data to a buffer memory 105 through DMA transfer. Then the CPU101 sets an indication to an interruption port 107 so that a CPU102 fetches the data of the memory 105. Thus an interruption is produced to the CPU102 via an interruption port 108 based on said indication. Then the CPU102 transfers the data to a buffer memory 104 from the memory 105. The same procedure is carried out also in case the data stored in the memory 104 is transferred to the memory 103 by the CPU102.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data transfer method between memories in a multiprocessor system having multiple connected microprocessors.

[Prior art]

Conventionally, a multiprocessor system in which multiple microprocessors are connected on a one-to-one basis has two memories connected to each microprocessor, and one buffer memory connected to each microprocessor regardless of the direction of memory transfer. (had a rainbow formation).

Therefore, when data is transferred between memories, as with half-duplex communication, collisions of transferred data and waits for data reception from the other party's microprocessor occur at the time of transmission. It had the disadvantage of being a complex C2. If these drawbacks are to be eliminated, complex processing such as programmable transmission control procedures and periodic programs; two-way polling processing, etc.1. It is necessary to have a capability.

[Purpose of the invention]

The purpose of the present invention is to eliminate (= avoid adding) complex processing capabilities, improve the efficiency of transfer data as well as full-duplex communication, and eliminate data transmission/reception ('ffl waiting time? The object of the present invention is to provide a memory-to-memory data transfer method that allows easy detection of data.

[A1j Formation of the Invention] The present invention (=the memory transfer method according to the present invention) includes a plurality of microprocessors provided one-to-one, and the microprocessor C.
, Qlj, and performs data transfer between the memories, the feature is that the microprocessor is individually connected to the microprocessor. an interrupt port for notifying the data transfer request from one microprocessor to the other microprocessor, and a buffer memory connected between the memories each time data is transferred; The processor receives the notification from the interrupt port and transfers data between the memories via the buffer memory corresponding to the direction in which data should be transferred.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to -.

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention. Here, 101 and 102 are microprocessors provided on a one-to-one basis, 106 and 104 are memories connected to the microprocessors 101 and 102, respectively, and 105 is a memory for transferring data from the memory 106 to the memory 104. A buffer memory 106 is a buffer memory for transferring data from the memory 104 to the memory 106, and 107 and 108 are connected to the microprocessors 101 and 1021, respectively, and are connected to each other (=
is also a connected interrupt port.

Next, the operation of this embodiment will be explained for each memory transfer event.

As a first η1 phenomenon, a case where the microprocessor f101 transfers data in the memory 106 to the memory 104 will be described. In this case, the microprocessor f101 transfers the data to be transferred to the buffer memory 105 by a general MA transfer. At this time, the status of whether the buffer memory 105 is empty or full is obvious to the microprocessor 101, and the above transfer is not made to wait at all. After that, Microprosen f101
Buffer memory 10 for micro processor 102
107 (Interrupted to get the data of 5)
+- Set an instruction to that effect. Then, interrupt port 10
An interrupt based on the above instruction (=) is generated in the microprocessor 102 via the microprocessor 8.
02 receives data from the buffer memory 105 to the memory 104 by DMA transfer according to the above instruction. At this time, the method for the microprocessor 102 to detect the above instruction is to set up an interrupt routine that is a simple process.
All you need to do is understand the above instructions.

Next, the microprocessor 102
When transferring data in the memory 104 to the memory 106, two Cs will be explained. In this case as well, similarly to the first event, the microprocessor 102 transfers the data to the D
The data is transferred to the buffer memory 106 by MA transfer, and an instruction to that effect is set for the microprocessor f101 to receive the data from the buffer memory 106 (interrupt baud) 108E. Then, an interrupt occurs in the microprocessor 101E via interrupt port 1 (J7) based on the above instruction.Then, the microprocessor 101 transfers data from the buffer memory 106 to the memory 103 by DMA transfer according to the above instruction. Take over.

Next, as an fJ3 event, Microprocene Su101
A case will be described in which the data transmission request from the microprocessor 102 and η() occur at the same time.

In this case, since the memory 106 and the memory 104 are separated in both directions (transmission/reception 1d) as if there were two normal transmission lines, microprocessor sensor f1U1 and microprocessor sensor f102 are separated to prevent data collision. can cause the first and second events of the Upper Era at the same time.

〔Effect of the invention〕

As explained above, the present invention provides a buffer memory for each data transfer direction between each memory so that both are homogeneous.
In addition, by providing an interrupt port to notify requests for data transfer, similar to the evolution of full duplex, it is possible to prevent the transfer data from colliding,
It is possible to eliminate the waiting time of i, and to detect the presence of H data without the need for redundant programming/processing.
・4 It has the effect of being easy to do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system configuration according to an embodiment of the present invention. 101.102...Microprocessor, 103.1
04...Memory, 105.106...Buffer memory, 107, 1
08... Harikomi Bo - To Patent Applicant NEC Co., Ltd. Representative Figure 1 0 Convex

Claims (1)

[Scope of Claims] A computer comprising a plurality of microprocessors arranged one-to-one and memories individually connected to the microprocessors,
In a multiprocessor system that transfers data between the memories, an interrupt port that is individually connected to the microprocessors and notifies a request for the data transfer from one microprocessor to another microprocessor, and an interrupt port that transfers data between the memories. and a buffer memory connected for each transfer direction, wherein the microprocessor receives the notification from the interrupt port and transfers data between the memories via the buffer memory corresponding to the direction in which data is to be transferred. A memory-to-memory data transfer method characterized by data transfer.