JPS6320555A - Inter-computer communication system - Google Patents
Inter-computer communication systemInfo
- Publication number
- JPS6320555A JPS6320555A JP16496186A JP16496186A JPS6320555A JP S6320555 A JPS6320555 A JP S6320555A JP 16496186 A JP16496186 A JP 16496186A JP 16496186 A JP16496186 A JP 16496186A JP S6320555 A JPS6320555 A JP S6320555A
- Authority
- JP
- Japan
- Prior art keywords
- communication
- computer
- area
- data
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006854 communication Effects 0.000 title claims abstract description 77
- 238000004891 communication Methods 0.000 title claims abstract description 75
- 230000004044 response Effects 0.000 claims abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 11
- 238000000034 method Methods 0.000 description 9
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 125000000174 L-prolyl group Chemical group [H]N1C([H])([H])C([H])([H])C([H])([H])[C@@]1([H])C(*)=O 0.000 description 1
- 102100030551 Protein MEMO1 Human genes 0.000 description 1
- 101710176845 Protein MEMO1 Proteins 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
【発明の詳細な説明】 〔概 要〕 複数の計算機間の通信の改良方式である。[Detailed description of the invention] 〔overview〕 This is an improved method of communication between multiple computers.
各計算機の主記憶装置には、各計算機に対応する所定の
記憶領域がある。共用の通信機構には同じ構成の領域か
らなる共用メモリがあり、通信要求元の宛先対応領域か
ら共用メモリの対応領域へデータを転送して、宛先計算
機へ割込で通知し、宛先が応答すると共用メモリから宛
先主記憶装置の所定領域へデータを転送する。The main storage device of each computer has a predetermined storage area corresponding to each computer. The shared communication mechanism has a shared memory consisting of areas with the same configuration, and data is transferred from the destination corresponding area of the communication request source to the corresponding area of the shared memory, and the destination computer is notified by interrupt, and when the destination responds. Transfer data from the shared memory to a predetermined area of the destination main storage device.
この方式により、高速の計算機関通信を、各計算機の少
ない通信オーバヘッドで可能にする。This method enables high-speed computer communication with less communication overhead on each computer.
本発明は、複数の計算機を有するシステムにおける、計
算機関通信の方式に関する。TECHNICAL FIELD The present invention relates to a method of computer communication in a system having a plurality of computers.
複数の独立に稼動する計算機を、適当な通信手段で結合
した、いわゆる疎結合マルチプロセッサシステムにおい
ては、計算機関通信の性能がシステムの処理効率に影響
する。In a so-called loosely coupled multiprocessor system in which a plurality of independently operating computers are connected through appropriate communication means, the performance of computer communication affects the processing efficiency of the system.
〔従来の技術と発明が解決しようとする問題点〕疎結合
マルチプロセッサシステムの計算機関通信手段には、例
えば第２図（ａ）のように複数の計算機１を、通信制御
装置２を経て通常の通信回線３で接続する方式、（ｂ）
のように計算機１をループ結合装置４により、光通信路
５等によるループ回線に接続して相互通信を行う方式等
がある。[Problems to be Solved by the Prior Art and the Invention] In the computer communication means of a loosely coupled multiprocessor system, a plurality of computers 1 are normally connected via a communication control device 2, as shown in FIG. 2(a). A method of connecting via communication line 3, (b)
There is a method in which the computer 1 is connected to a loop line such as an optical communication path 5 using a loop coupling device 4 to perform mutual communication, as shown in FIG.
又、第２図（Ｃ）は各計算機１のチャネル装置６間を、
いわゆるチャネル間結合装置７で接続して、各計算機１
の主記憶装置間のデータ転送により通信を行う方式であ
る。Moreover, FIG. 2(C) shows the connection between the channel devices 6 of each computer 1,
Each computer 1 is connected by a so-called inter-channel coupling device 7.
This method performs communication by transferring data between main storage devices.
第２図（ｄ）は各計算機１が磁気ディスク記憶装置のよ
うな外部記憶装置９を共用する方式であり、８は制御装
置である。FIG. 2(d) shows a system in which each computer 1 shares an external storage device 9 such as a magnetic disk storage device, and 8 is a control device.
それらの通信方式は、それぞれ公知の特徴を持って、計
算機間の通信を処理することができるが、通信速度の向
上、及び通信制御のための計算機１の処理負荷量である
通信オーバヘッドの軽減、あるいは通信の両端の同期化
処理の削減等による処理効率の改善が望まれていた。Each of these communication methods has well-known characteristics and can process communication between computers. Alternatively, it has been desired to improve processing efficiency by reducing synchronization processing at both ends of communication.
第１図は、本発明の構成を示すブロック図である。 FIG. 1 is a block diagram showing the configuration of the present invention.
図において、１０は通信機構、２０は計算機であり、通
信機構１０の１１は制御部、１２は共用メモリ、１３は
転送制御部を示し、計算機２０の２１は中央処理装置（
ＣＰＵ）、２２は主記憶装置、２４は通信領域を示す。In the figure, 10 is a communication mechanism, 20 is a computer, 11 of the communication mechanism 10 is a control unit, 12 is a shared memory, 13 is a transfer control unit, and 21 of the computer 20 is a central processing unit (
22 is a main storage device, and 24 is a communication area.
疎結合マルチプロセッサシステムを構成する各計算機２
０の主記憶装置２２の記憶領域には、同じ領域構成の通
信領域２４が設けられ、各通信領域２４は、このシステ
ムの各計算機２０に割り当てられたブロックに分割され
ている。Each computer 2 that constitutes a loosely coupled multiprocessor system
Communication areas 24 having the same area configuration are provided in the storage area of the main storage device 22 of No. 0, and each communication area 24 is divided into blocks assigned to each computer 20 of this system.
通信機構１０には、通信領域２４と同一の構成の記憶領
域からなる共用メモリ１２を設け、転送制御部１３を経
て、すべての主記憶袋Ｗ２２と接続し、転送制御部１３
の制？ｆｌによって主記憶装置２２の通信多頁域２４と
共用メモリとの対応ブロック間でデータ転送が可能なよ
うに構成されている。The communication mechanism 10 is provided with a shared memory 12 consisting of a storage area having the same configuration as the communication area 24, and is connected to all the main memory bags W22 via the transfer control unit 13.
The system? fl allows data transfer between corresponding blocks of the communication multi-page area 24 of the main storage device 22 and the shared memory.
計算機間の通信を行う場合、発信側の計算機２０では、
ＣＰＵ２１が通信領域２４の、宛先の計算機２０に対応
するブロックに送信データを書込み、通信機ｆ１１０に
送信要求を送る。When communicating between computers, the sending computer 20:
The CPU 21 writes transmission data to a block corresponding to the destination computer 20 in the communication area 24, and sends a transmission request to the communication device f110.
通信機構１０の制御部１１がこの要求を受信し、通信が
可能の状態であれば、要求元の通信領域２４の、宛先対
応ブロックの送信データを、共用メモリ１２の同じブロ
ックに転送し、宛先のＣＰ Ｕ２１に割込要求を送る。The control unit 11 of the communication mechanism 10 receives this request, and if communication is possible, transfers the transmission data of the block corresponding to the destination in the communication area 24 of the request source to the same block of the shared memory 12, and An interrupt request is sent to the CPU 21 of.
宛先のＣＰ Ｕ２１は割込によって、メツセージ受信の
必要を知ると、受信可能の状態にして通信機構１０に応
答し、その応答により通信機構１０では、共用メモ１月
２の宛先対応ブロックから、宛先の通信領域２４の同じ
ブロックへデータを転送して、この通信の処理を終わる
。When the destination CPU 21 learns of the need to receive a message through an interrupt, it responds to the communication mechanism 10 by setting it in a receivable state. The data is transferred to the same block in the communication area 24 of , and the communication process ends.
以上の方式により、各計算機２０のＣＰＵ２１は比較的
単純な通信処理によって計算機関通信が可能になり、デ
ータの転送は主記憶装置のアクセス速度に近い速度にす
ることができる。With the above method, the CPU 21 of each computer 20 can perform computer communication through relatively simple communication processing, and data transfer can be performed at a speed close to the access speed of the main storage device.
第１図において、疎結合マルチプロセッサシステムを構
成する各計算機２０を、説明の都合により図示のように
計算機Ａ、Ｂ、Ｃ及びＤと呼ぶものとする。In FIG. 1, each computer 20 constituting the loosely coupled multiprocessor system will be referred to as computers A, B, C, and D as shown for convenience of explanation.
各計算機２０の主記憶装置２２の記憶領域の一部に、同
一領域構成の通信領域２４が設けられる。A communication area 24 having the same area configuration is provided in a part of the storage area of the main storage device 22 of each computer 20.
各通信領域２４は、図に分割してＡ−Ｄとして示すよう
に、このシステムの計算機Ａ−Ｄに割り当てられたブロ
ックに分割される。Each communication area 24 is divided into blocks assigned to computers A to D of this system, as shown in the diagram as divided A to D.
各ブロックは後に説明するように、その所属する計算機
Ａ−Ｄ自身に対応するブロック （同名のブロック）が
、その計算機宛のデータの受信領域として使用され、゛
その他のブロックはそれぞれの計算機宛送信データを保
持する領域とされる。As will be explained later, the blocks corresponding to the computers A to D to which they belong (blocks with the same name) are used as receiving areas for data addressed to that computer, and the other blocks are used to send data to each computer. This area is used to hold data.
通信機構１０には、通信領域２４と同一構成の記憶領域
からなる共用メモ１月２を設ける。それらの各ブロック
Ａ−Ｄは、後述のように同名の計算機２０宛送信データ
の中継バッファとなる。The communication mechanism 10 is provided with a shared memo 2 consisting of a storage area having the same configuration as the communication area 24. Each of these blocks A to D serves as a relay buffer for transmission data addressed to the computer 20 with the same name, as will be described later.
共用メモ１月２は転送制御部１３を経て、すべての主記
憶装置２２と接続し、転送制９■部１３の制御によって
主記憶装置２２の通信領域２４と共用メモリ１２との対
応ブロック （Ａ対応ブロック、Ｂ対応ブロック等）の
間で、メモリ間データ転送が可能なように構成されてい
る。The shared memo 1/2 is connected to all the main storage devices 22 via the transfer control section 13, and under the control of the transfer control section 13, a corresponding block (A B-corresponding blocks, B-corresponding blocks, etc.) are configured to enable inter-memory data transfer.
例えば計算機Ａから計算ＫＩＢへメツセージを送る通信
の場合、発信側の計算機２０ （Ａ）ではｃｐｔＪ２１
が、自身の主記憶装置２２の通信領域２４上の、宛先の
計算機２０（Ｂ）に対応するブロックＢにメツセージを
書込み、通信機構１０の制御部１１に送信要求を送る。For example, in the case of communication that sends a message from computer A to calculation KIB, cptJ21
writes a message to block B corresponding to the destination computer 20 (B) on the communication area 24 of its own main storage device 22, and sends a transmission request to the control unit 11 of the communication mechanism 10.
制御部１１はこの送信要求を受信し、送信要求で指定さ
れる宛先計算機２０と通信が可能の状態かチェックする
。The control unit 11 receives this transmission request and checks whether communication is possible with the destination computer 20 specified in the transmission request.
この場合、共用メモ１Ｊ１２の宛先計算機Ｂに対応する
ブロックＢが空きであれば通信可能であるが、例えばブ
ロックＢが、他の計算機Ｃ，Ｄ等から送信されたデータ
を保持して未だ送出していない場合、あるいは他に始め
られた通信の処理中の場合等は、現要求の処理を待つ必
要がある。In this case, if block B corresponding to the destination computer B of the shared memo 1J12 is free, communication is possible, but for example, block B holds data sent from other computers C, D, etc. and is not yet sent. If the current request is not being processed, or if some other communication is being processed, it is necessary to wait for the current request to be processed.
通信可能の場合、；ν制御部１１は転送＄ｒ！Ｉ ８０
部１３に指示して、要求元計算機Ａの通信領域２４の、
宛先対応ブロックＢに書き込まれているデータを、共用
メモリ１２の同じブロックＢに転送する。If communication is possible, ;ν control unit 11 transfers $r! I 80
13, the communication area 24 of the requesting computer A,
The data written in the destination corresponding block B is transferred to the same block B in the shared memory 12.
その後制御部１１は、宛先の計算機のＣＰ ０２１に所
定の例えばアテンション割込を発生するための割込要求
信号を、計算機ＢのＣＰ Ｕ２１に送る。Thereafter, the control unit 11 sends to the CPU 21 of the computer B an interrupt request signal for generating a predetermined attention interrupt, for example, to the CP 021 of the destination computer.
計算機ＢのＣＰＵ２１はアテンション割込を処理するこ
とによって、受信すべきメソセージがあることを知ると
、例えばその通信領域２４のブロックＢに以前に受信し
た未処理のデータがあれば、他の領域へ転送する等の処
置をして、プロ、りＢをデータ受信可能の状態にして、
通信機構１０に受信可能を示す応答をする。When the CPU 21 of the computer B learns that there is a message to be received by processing the attention interrupt, for example, if there is previously received unprocessed data in the block B of the communication area 24, the CPU 21 transfers the message to another area. Take steps such as transferring the data to make the Pro/RiB ready to receive data.
A response is sent to the communication mechanism 10 indicating that reception is possible.
通信機構１０の制御部１１はその応答を受けると、転送
制御■部１３に指示して、共用メモ１月２の宛先対応プ
ロ７りＢから、宛先計算機Ｂの通信領域２４の同じブロ
ックＢヘデータを転送する。When the control unit 11 of the communication mechanism 10 receives the response, it instructs the transfer control unit 13 to transfer the data from the destination support program B of the shared memo January 2 to the same block B of the communication area 24 of the destination computer B. Transfer.
転送を完了すれば共用メモリ１２のブロックＢは空き状
態とし、この通信の処理を終わる。When the transfer is completed, block B of the shared memory 12 becomes empty, and this communication process ends.
以上の説明から明らかなように、本発明によれば、疎結
合マルチプロセッサシステムの計算機関通信の通信処理
オーバヘッドが削減され、データ転送が高速化されるの
で、システムの処理効率を向上するという著しい工業的
効果がある。As is clear from the above description, according to the present invention, the communication processing overhead of computing engine communication in a loosely coupled multiprocessor system is reduced and data transfer is accelerated, which significantly improves the processing efficiency of the system. It has industrial effects.
第１図は本発明の構成を示すブロック図、第２図は従来
の構成例ブロック図である。
図において、
１．２０は計算機、 ２は通信制御装置、３は通信
回線、 ４はループ結合装置、５は光通信路、
６はチャネル装置、７はチャネル間結合装置
、
８は制御装置、 ９は外部記憶装置、１０は通
信機構、 １１は制御部、１２は共用メモリ、
１３は転送制御部、２１はＣＰＵ、 ２２
ハ主記１！ 装置、２４は通信領域を示す０．！FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a block diagram of a conventional configuration example. In the figure, 1.20 is a computer, 2 is a communication control device, 3 is a communication line, 4 is a loop coupling device, 5 is an optical communication path,
6 is a channel device, 7 is an inter-channel coupling device, 8 is a control device, 9 is an external storage device, 10 is a communication mechanism, 11 is a control unit, 12 is a shared memory,
13 is a transfer control unit, 21 is a CPU, 22
Ha main record 1! 0.24 indicates the communication area. !
Claims (1)
計算機（２０）と接続し、共用メモリ（１２）を有する
通信機構（１０）を設け、 該通信機構（１０）は、該計算機（２０）からの通信要
求を受け付けて、該要求元計算機の主記憶装置上の宛先
計算機ごとの所定記憶領域（２４）から、前記共用メモ
リ（１２）上の宛先計算機ごとの所定記憶領域へデータ
を転送し、 該宛先計算機（２０）へ所定の割込を発生する割込要求
信号を送出し、 該宛先計算機（２０）からの所定の応答信号を受信して
、該共用メモリ（１２）上に保持するデータを、該宛先
計算機の主記憶装置上の所定記憶領域（２４）へ転送す
るように構成されていることを特徴とする計算機間通信
方式。[Claims] In mutual communication between a plurality of computers (20), a communication mechanism (10) connected to the plurality of computers (20) and having a shared memory (12) is provided, the communication mechanism (10) receives a communication request from the computer (20), and from a predetermined storage area (24) for each destination computer on the main storage of the requesting computer, a predetermined storage area for each destination computer on the shared memory (12). Transfer the data to the storage area, send an interrupt request signal that generates a predetermined interrupt to the destination computer (20), receive a predetermined response signal from the destination computer (20), and transfer the data to the shared memory. (12) An intercomputer communication system characterized in that the data held on the computer is transferred to a predetermined storage area (24) on the main storage device of the destination computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16496186A JPS6320555A (en) | 1986-07-14 | 1986-07-14 | Inter-computer communication system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16496186A JPS6320555A (en) | 1986-07-14 | 1986-07-14 | Inter-computer communication system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6320555A true JPS6320555A (en) | 1988-01-28 |
| JPH0511341B2 JPH0511341B2 (en) | 1993-02-15 |
Family
ID=15803157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16496186A Granted JPS6320555A (en) | 1986-07-14 | 1986-07-14 | Inter-computer communication system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6320555A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01233651A (en) * | 1988-03-15 | 1989-09-19 | Fujitsu Ltd | Communication control system |
| JP2006342941A (en) * | 2005-06-10 | 2006-12-21 | Jtekt Corp | Mounting structure for driving force transmission device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010198335A (en) * | 2009-02-25 | 2010-09-09 | Toshiba Corp | Software automatic-test apparatus and method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55131829A (en) * | 1979-03-30 | 1980-10-14 | Toshiba Corp | Transfer system of shared memory under communication control |
| JPS5730065A (en) * | 1980-07-30 | 1982-02-18 | Fujitsu Ltd | Data transfer system |
-
1986
- 1986-07-14 JP JP16496186A patent/JPS6320555A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55131829A (en) * | 1979-03-30 | 1980-10-14 | Toshiba Corp | Transfer system of shared memory under communication control |
| JPS5730065A (en) * | 1980-07-30 | 1982-02-18 | Fujitsu Ltd | Data transfer system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01233651A (en) * | 1988-03-15 | 1989-09-19 | Fujitsu Ltd | Communication control system |
| JP2006342941A (en) * | 2005-06-10 | 2006-12-21 | Jtekt Corp | Mounting structure for driving force transmission device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0511341B2 (en) | 1993-02-15 |
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