JPS6020270A - Data transfer system - Google Patents

Abstract

PURPOSE:To prevent invalid use of the memory area of a memory by transferring release signals to a signal holder together with disposing data which are not transferred to a data transmission unit when data transfer, which exceeds the prescribed word number, is required. CONSTITUTION:When data transfer, which exceeds the prescribed word number, is required, the processor PU judges transfer data to be abnormal, disposes data which are not transferred held by the data transmission unit ADLC, and initially sets again the address inside the memory MEM which transfer data to be stored in the direct memory access controller DMAC and word numbers which are not transferred. At the same time, the processor PU transfers the release signal to the signal holder HLD through the common bus BUS, and releases the synchronous demand signal S2. As a result, the synchronous transfer demand signal S2 is not transferred to the direct memory access controller DMAC, and data is not transferred by the direct memory access controller DMAC until the transfer demand signal S1 is again transferred to the signal holder HLD.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a data transfer system, and more particularly to a data transfer method that prevents invalid use of a transfer data storage area of a storage device.

(b) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional data transfer method in this type of data transfer system. In FIG. 1, the first device is a direct memory access control device DMAC, and the second device is a data transmission device ADLC.
However, a signal holding device HLD is also provided as a third device. When data arrives from the transmission path, the data transmission device ADLC transmits a transfer request signal sl to the signal holding device HLD. The signal holding device HLD to which the transfer request signal s1 has been transmitted holds the synchronous transfer request signal s2 synchronized with the clock signal governing the operation of the direct memory access control device DMAC, and transmits it to the direct memory access control device DMAC. The direct memory access control device DMAC has the address in the storage device MEM where the transfer data should be stored and the number of transferable words initialized in advance by the processor PU, and when it receives the synchronous transfer request signal S2, it controls the data transfer device ADLC. One word of data is stored in the storage device MEM via the common bus Bus.
is transferred to a predetermined address, the address and the number of transferable words are updated, and a transfer execution signal S is sent to the signal holding devices H1 and D.
Convey 3. The signal holding device HLD holds the transfer execution signal S3
When the synchronous transfer request signal S2 is transmitted, the held synchronous transfer request signal S2 is restored.

If the data transmission device ADLC holds further data to be transferred, the transfer request signal S1 is subsequently transmitted to the signal holding device HLD. As a result, the signal holding device HLD
outputs and holds the synchronous transfer request signal S2 again, and transmits it to the direct memory access control device DMAC. The direct memory access control device DMAC, which has received the synchronous transfer request signal S2, transfers one word of data to the storage word W in the same manner as described above.
Transfer to a predetermined address of MEM. When the direct memory access control device DMAC has finished transferring data equal to the number of transferable words in this manner, it notifies the processor PU to that effect. Note that if the data transmission device ADLC retains untransferred data, the transfer request signal S1 continues to be sent to the signal holding device HLD even after the direct memory access control device DMAC has transferred data equal to the number of transferable words. The signal holding device HLD outputs and holds the synchronous transfer request signal s2 and transmits it to the direct memory access control device DMAC, but the direct memory access control device DMAC does not transfer data exceeding the number of transferable words. On the other hand, the processor PU, which has been notified by the direct memory access control device DMAC of the completion of transfer of data equal to the number of transferable words, transfers data to the data transmission device ADL.
Since C has a larger amount of transferred data than expected, it determines that the transferred data is a foreign item, and the data transmission device ADL
The untransferred data held by C is discarded, and the address in the storage device MEM where the transfer data is to be stored and the number of transferable words are again initialized in the direct memory access control device DMAC. The data transmission device ADLC, which has discarded its untransferred data, is transferred to the signal holding device HLD.
The transfer request signal S1 that was being transmitted to the direct memory access control device D is stopped, but the signal holding device HLD is transferred to the direct memory access control device D.
Since the transfer execution signal S3 is not transmitted from the MAC, it continues to hold the synchronous transfer request signal S2 and transmits it to the direct memory access control device DMAC. As a result, the direct memory access control value WDMAC transfers invalid data from the data transmission device ADLC that does not hold the data to be transferred to a predetermined address of the one-word storage device MEM, updates the address and the number of transferable words, and The transfer execution signal s3 is transmitted to the signal holding device HLD, and the synchronous transfer request signal S2 is restored.

As is clear from the above explanation, in a conventional data transfer method, the direct memory access control device DMA
If the data transmission device ADLC retains untransferred data even after C has finished transferring the data of the transferable number of words, the signal retention device HLD sends a synchronous transfer request signal even though the processor PU discards the untransferred data. In order to transmit S2 to the direct memory access control device DMAC, the direct memory access control device DMAC transfers the invalid data to the one-word memorization device MEM, and the memory device MEM
This results in an invalid use of storage space.

(C) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional data transfer method as described above and to realize a means for preventing the first device from using the storage area of the storage device invalidly. is in

(d) Structure of the Invention This object is to provide a first device that controls the transfer of data of a predetermined number of words independently of the processor, and a transfer request signal from a second device that requests the second device to transfer data. a third device that transmits and holds the transfer request signal to the first device, and restores the held transfer request signal when receiving a transfer execution signal indicating that one word of data has been transferred from the first device; and if the first device is requested to transfer data exceeding a predetermined number of words, after the first device transfers the predetermined number of words, the processor of the second device In a data transfer system that discards untransferred data held by the second device, when the processor discards the untransferred data held by the second device, means is provided for restoring a transfer request signal held by the third device. This is achieved by

tel　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a data transfer method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, a transfer execution signal S3 is transmitted from the direct memory access control device DMAC to the signal holding device HLD via a gate G, and a recovery signal s4 is transmitted from the input/output device IO connected to the common bus BUS. It is transmitted via game 1-G. Also in FIG. 2, the direct memory access control device DMAC stores the transfer data held by the data transmission device ADLC in a predetermined address of the storage device MEM for one word in the same process as in FIG. When the transfer is completed, the processor PU is notified to that effect, and thereafter, the data transmission device ADμC transmits the transfer request signal S1 to the signal holding device HLD, and the signal holding device HLD transmits the synchronous transfer request signal S2 to the direct memory access control device. Even if it is transmitted to DMAC,
No data is transferred. In such a state, the processor P
As shown in FIG. 1, since the data transmission device ADLC has a larger amount of transferred data than expected,
The data transmission device ADLC determines that the transferred data is abnormal.
discards the untransferred data held by the direct memory access control device DMAC, initializes the address in the storage device MEM where the transfer data is to be stored and the number of transferable words in the direct memory access control device DMAC, and also discards the untransferred data held by the input/output device IO via the common bus BUS. and control the signal holding bag ff1H via game 1-G.
The recovery signal S4 is transmitted to the LD. The signal holding device HLD to which the recovery signal S4 has been transmitted receives the synchronous transfer request signal S2.
to restore. As a result, the synchronous transfer request signal s2 is no longer transmitted to the direct memory access control device DMAC, the data transmission device ADLC retains the data to be newly transferred, and the transfer request signal S1 is transmitted again to the signal holding device HLD.
Direct memory access control device DM
AC never transfers data.

As is clear from the above description, according to the present embodiment, the processor PU causes the data transmission device ADLC to discard untransferred data, and also causes the input/output device IO to discard untransferred data.
In order to transmit the recovery signal S4 to the LD, the data transmission device A
Even though the DLC does not hold the data to be transferred, the synchronous transfer request signal S2 is transmitted to the direct memory access control device DMAC, and the direct memory access control device DMAC stores the invalid data in the storage devices M and EM. It can be avoided.

Note that FIG. 2 is only one embodiment of the present invention, and for example, the first, second, and third devices are not limited to those shown in the drawings, and may be modified in many other ways. However, the effects of the present invention do not change in either case. It goes without saying that the data transfer system to which the present invention is applied is not limited to that shown in the drawings.

(fl) Effects of the Invention As described above, according to the present invention, in the data transfer system, it is possible to prevent the - amount of devices from ineffectively using the storage area of the storage device, and the utilization rate of the storage device is improved.

[Brief explanation of drawings]

Figure 1 shows an example of a conventional data transfer method, Figure 2 shows an example of a conventional data transfer method.
The figure is a diagram showing a data transfer method according to an embodiment of the present invention. In the figure, ADLC is a data transmission device, BUS is a common bus, DMAC is a direct memory access control device,
G is a gate, HLD is a signal holding device, ■0 is an input/output device, L is a transmission line, MEM is a storage device, PU is a processor,
sl is a transfer request signal, s2 is a synchronous transfer request signal, s3 is a transfer execution signal, and s4 is a recovery signal.

Claims (1)

[Claims] A first device that controls the transfer of data of a predetermined number of words independently of the processor, and a second device that requests the second device to transfer data, transmits and holds a transfer request signal to the first device. a third device that restores the held transfer request signal upon receiving a transfer execution signal indicating that one word of data has been transferred from the first device; In the data transfer system, when a data transfer exceeding the number of words is requested, the first device transfers the data of the predetermined number of words, and then the processor discards the untransferred data held by the second device, A data transfer system characterized by providing means for restoring a transfer request signal held by the third device when the processor discards untransferred data held by the second device.