JPS6154268B2 - - Google Patents

Info

Publication number
JPS6154268B2
JPS6154268B2 JP16601479A JP16601479A JPS6154268B2 JP S6154268 B2 JPS6154268 B2 JP S6154268B2 JP 16601479 A JP16601479 A JP 16601479A JP 16601479 A JP16601479 A JP 16601479A JP S6154268 B2 JPS6154268 B2 JP S6154268B2
Authority
JP
Japan
Prior art keywords
etching
diaphragm
semiconductor substrate
thickness
diffusion regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16601479A
Other languages
Japanese (ja)
Other versions
JPS5688372A (en
Inventor
Yutaka Mihashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16601479A priority Critical patent/JPS5688372A/en
Publication of JPS5688372A publication Critical patent/JPS5688372A/en
Publication of JPS6154268B2 publication Critical patent/JPS6154268B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Sensors (AREA)

Description

【発明の詳細な説明】 この発明は半導体圧力変換器に用いる半導体ダ
イヤフラムに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor diaphragm for use in a semiconductor pressure transducer.

半導体圧力変換器は、シリコン・ゲルマニウム
などの半導体結晶に応力を加えることによつて、
ピエゾ抵抗効果によりその電気的抵抗が変化する
のを利用したものであり、一般にこの種の半導体
圧力変換器では、シリコン結晶基板中に選択拡散
技術を用いてゲージ抵抗を形成すると共に、この
ゲージ抵抗形成部の厚さを薄くしてダイヤフラム
にしてあり、外部からの加圧力でダイヤフラムを
変形させ、そのピエゾ抵抗効果によるゲージ抵抗
の抵抗値変化から、加圧力を検出するようにして
いるのである。
Semiconductor pressure transducers are made by applying stress to semiconductor crystals such as silicon or germanium.
This type of semiconductor pressure transducer utilizes the change in electrical resistance caused by the piezoresistance effect, and generally, in this type of semiconductor pressure transducer, a gauge resistor is formed in a silicon crystal substrate using selective diffusion technology, and this gauge resistor is The thickness of the forming part is reduced to form a diaphragm, and the diaphragm is deformed by external pressure, and the pressure is detected from the change in the resistance value of the gauge resistance due to the piezoresistance effect.

従つてこのような半導体圧力変換器であつて
は、その特性ならびに再現性を良好にしてバラツ
キを少なくするために、ダイヤフラムを所定の厚
さに精度よく形成することが必要とされる。従
来、このダイヤフラムの厚さ形成には、通常、化
学的エツチング法を適用しているが、この手段で
はエツチング液の温度,組成,撹拌状態などによ
つて、そのエツチング速度が著るしく影響され、
1回エツチングでダイヤフラムを所定の厚さに形
成することができず、エツチングを数回繰り返
し、かつその度毎に厚さを測定するようにして所
期の厚さを得ており、極めて手間のかかるもので
あつた。
Therefore, in such a semiconductor pressure transducer, in order to improve its characteristics and reproducibility and reduce variations, it is necessary to form the diaphragm to a predetermined thickness with high precision. Conventionally, a chemical etching method has usually been applied to form the thickness of this diaphragm, but with this method, the etching speed is significantly affected by the temperature, composition, stirring state, etc. of the etching solution. ,
It was not possible to form the diaphragm to the desired thickness by one-time etching, so etching was repeated several times and the thickness was measured each time to obtain the desired thickness, which was extremely time-consuming. It was something like that.

この発明は従来のこのような実情に鑑み、ダイ
ヤフラムのエツチングに際して、これが所定の厚
さまでエツチングされたことを検出し得るように
して、エツチングによるダイヤフラムの厚さ設定
を容易にしたものである。
In view of these conventional circumstances, the present invention makes it possible to detect when a diaphragm has been etched to a predetermined thickness, thereby making it easier to set the thickness of the diaphragm by etching.

以下、この発明方法の一実施例につき、添付図
面を参照して詳細に説明する。
Hereinafter, one embodiment of the method of this invention will be described in detail with reference to the accompanying drawings.

第1図a,bはこの実施例によるダイヤフラム
のエツチング開始時を終了時とを示しており、こ
れらの各図において、はダイヤフラムとなるn
形シリコン半導体基板、2は拡散マスクに用いた
シリコン酸化膜などの表面保護膜、3,5および
4,6は前記n形シリコン半導体基板に、表面
からの拡散深さが目的とするダイヤフラム厚さと
なるように比較的深く選択拡散させたボロンなど
のp形拡散散領域およびそのpn接合であり、こ
の拡散深さは、ボロンなどのデポジシヨン条件お
よびその後のドライブ工程の温度,時間などをき
びしく制御することで、比較的高精度にしかも再
現性,制御性よく設定し得る。また7,8はこの
p形拡散領域3,5に設けられたアルミニウムな
どの電極、9は前記n形シリコン半導体基板
形成されたゲージ抵抗となる拡散深さが前記領域
3,5よりも浅いp形拡散領域、10はこられの
各拡散領域3,5,9の直下に開口部を有して形
成されたエツチングマスク、11,12,13は
前記各電極7,8間にリード線14で直列に接続
された直流電源,電流計,電流調節用の可変低
抗、15は例えば弗酸,硝酸系あるいはKOH,
NaOHなどのアルカリ系の電解質エツチング液で
ある。
Figures 1a and 1b show the beginning and end of etching of the diaphragm according to this embodiment, and in each of these figures, 1 indicates n, which is the diaphragm.
2 is a surface protective film such as a silicon oxide film used as a diffusion mask, 3, 5 and 4, 6 are the n-type silicon semiconductor substrate 1 , and the diffusion depth from the surface is the desired diaphragm thickness. This is a p-type diffused region of boron, etc., which is selectively diffused relatively deeply to ensure a relatively deep diffusion, and its p-n junction. By doing so, settings can be made with relatively high accuracy and with good reproducibility and controllability. Further, reference numerals 7 and 8 refer to electrodes such as aluminum provided in the p-type diffusion regions 3 and 5, and reference numeral 9 refers to electrodes formed in the n-type silicon semiconductor substrate 1 , which have a diffusion depth deeper than that of the regions 3 and 5 and serve as gauge resistance. A shallow p-type diffusion region; 10 is an etching mask formed with an opening directly below each of these diffusion regions 3, 5, and 9; 11, 12, and 13 are lead wires between each of the electrodes 7 and 8; 14 is a DC power supply, an ammeter, and a variable resistor for controlling the current, which are connected in series; 15 is a hydrofluoric acid, nitric acid, or KOH,
This is an alkaline electrolyte etching solution such as NaOH.

ここで第1図aのように、表面保護膜2および
電極7,8などがエツチング液15に直接触れな
いようにしてエツチングを開始した時点では、深
いp形拡散領域3,5は露出しておらず、これに
図の極性で直流電圧を印加してあるために、領域
3のpn接合4は順方向バイアス、領域5のpn接
合6は逆方向バイアスとなつて、ブロツキングジ
ヤンクシヨンとして働き、pn接合6の逆方向ブ
レークダウン電圧よりも低い印加電圧としておく
ことで電流計12は振れないままにある。
Here, as shown in FIG. 1a, when etching is started while preventing the surface protection film 2, electrodes 7, 8, etc. from coming into direct contact with the etching solution 15, the deep p-type diffusion regions 3, 5 are not exposed. Since a DC voltage is applied to this with the polarity shown in the figure, the pn junction 4 in region 3 is forward biased, and the pn junction 6 in region 5 is biased in the reverse direction, resulting in a blocking junction. By keeping the applied voltage lower than the reverse breakdown voltage of the pn junction 6, the ammeter 12 does not swing.

前記状態でエツチングが進行し、第1図bのよ
うに深にp形拡散領域3,5が共に露出して電解
質のエツチング液15に触れると、pn接合4,
6はもはやブロツキングジヤンクシヨンとして働
かず、電流Aはエツチング液15を介して容易に
流れ、深いp形拡散領域3,5の位置までエツチ
ングが行なわれたことを、電流計12の振れによ
つて検出できるのである。そしてこのとき、この
p形拡散領域3,5の直下の部分のエツチングと
同時に、ゲージ抵抗であるp形拡散領域9の直下
の部分のエツチングも、そのエツチングマスク1
0の開口部形状および面積を同じにしておくこと
で、同速度で同様に行なわれる。従つて前記深い
p形拡散領域3,5の基板表面からの拡散深さ
を、目的とするダイヤフラム厚となるように設定
しておけば、電流計12の指示によつて、所定位
置までのエツチングがなされて、ゲージ抵抗部分
のダイヤフラムが所定厚さになつたことを検出し
得るのである。
When etching progresses in the above state and both the p-type diffusion regions 3 and 5 are exposed deeply and come into contact with the electrolyte etching solution 15 as shown in FIG.
6 no longer functions as a blocking junction, the current A flows easily through the etching solution 15, and the swing of the ammeter 12 indicates that etching has been carried out to the position of the deep p-type diffusion regions 3 and 5. Therefore, it can be detected. At this time, at the same time as the etching of the portion directly under the p-type diffusion regions 3 and 5, the etching of the portion directly under the p-type diffusion region 9, which is the gauge resistor, is also performed using the etching mask 1.
By keeping the opening shape and area of 0 the same, the same speed and similar operation can be performed. Therefore, if the diffusion depth of the deep p-type diffusion regions 3 and 5 from the substrate surface is set so that the desired diaphragm thickness is achieved, etching to a predetermined position can be performed according to the instruction from the ammeter 12. This makes it possible to detect that the diaphragm in the gauge resistance portion has reached a predetermined thickness.

なお前記実施例では、説明を判り易くするため
に、ゲージ抵抗を1ケ所にのみ形成した場合につ
いて述べたが、同一の基板中に同時に多数のゲー
ジ抵抗のあるダイヤフラムを形成できることは勿
論であり、また均一性を考慮して、エツチングを
モニタする深いp形拡散領域は、なるべく基板中
央部に配するのが望ましい。
In the above embodiment, in order to make the explanation easier to understand, the case where the gauge resistor is formed only in one place has been described, but it goes without saying that diaphragms with a large number of gauge resistors can be formed simultaneously on the same substrate. Further, in consideration of uniformity, it is desirable that the deep p-type diffusion region for monitoring etching be placed as close to the center of the substrate as possible.

また第2図は前記実施例でのエツチング装置の
具体例を示しており、エツチング容器16と保持
治具17とを用い、前記シリコン半導体基板
表面保護膜2側を、耐エツチング性のあるワツク
ス18により保持治具17に貼り付け保持させ、
この表面保護膜2および各電極7,8がエツチン
グ液15に触れないようにし、かつ各リード線1
4にも保護被覆19を施して、エツチング液15
をみたした容器16内に装入し、エツチングの均
一性をよくするために撹拌器20を配し、この状
態でエツチングするのである。
Further, FIG. 2 shows a specific example of the etching apparatus in the above embodiment, in which an etching container 16 and a holding jig 17 are used to coat the surface protection film 2 side of the silicon semiconductor substrate 1 with an etching-resistant etching material. It is pasted and held on the holding jig 17 with wax 18,
This surface protection film 2 and each electrode 7, 8 are prevented from coming into contact with the etching liquid 15, and each lead wire 1 is
A protective coating 19 is also applied to 4, and an etching solution 15 is applied.
The material is charged into a container 16 filled with water, and a stirrer 20 is provided to improve the uniformity of etching, and etching is performed in this state.

以上詳述したようにしてこの発明によるとき
は、ゲージ抵抗を設けた素材半導体基板をエツチ
ングによりダイヤフラムに形成するに際して、エ
ツチング液の温度,組成,撹拌状態などが、たと
えば変化した場合においても、容易に所定厚さの
ダイヤフラムをエツチング形成し得るものであ
り、従つてこの種の半導体圧力変換器に用いる半
導体ダイヤフラムを、高精度でしかも再現性,制
御性よく製造することが可能となり、コストダウ
ンを図り得るなどの特長を有するものである。
As described in detail above, according to the present invention, when forming a diaphragm by etching a raw semiconductor substrate provided with a gauge resistor, even if the temperature, composition, stirring state, etc. of the etching solution change, for example, it can be easily etched. It is possible to form a diaphragm of a predetermined thickness by etching the semiconductor diaphragm used in this type of semiconductor pressure transducer, making it possible to manufacture semiconductor diaphragms with high precision, reproducibility, and controllability, thereby reducing costs. It has the following features:

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aおよびbはこの発明方法の一実施例を
適用したダイヤフラムのエツチング開始時および
終了時の状態を示す各々断面説明図、第2図は同
上エツチング装置の具体的構成例を示す断面図で
ある。 ……n形シリコン半導体基板、2……表面保
護膜、3,5……深いp形拡散領域(モニタ領
域)、4,6……pn接合、7,8……電極、9…
…浅いp形拡散領域(ゲージ抵抗領域)、10…
…エツチングマスク、15……導電性のあるエツ
チング液。
FIGS. 1a and 1b are explanatory cross-sectional views showing the states at the start and end of etching of a diaphragm to which an embodiment of the method of the present invention is applied, and FIG. 2 is a cross-sectional view showing a specific example of the configuration of the same etching apparatus. It is. 1 ...N-type silicon semiconductor substrate, 2...Surface protective film, 3, 5...Deep p-type diffusion region (monitor region), 4,6...PN junction, 7, 8...Electrode, 9...
...shallow p-type diffusion region (gauge resistance region), 10...
... Etching mask, 15... Conductive etching liquid.

Claims (1)

【特許請求の範囲】[Claims] 1 表面側にゲージ抵抗を形成した一方の導電形
の半導体基板を有し、この半導体基板の一部に表
面側から、得ようとするダイヤフラムの厚さに等
しい拡散深さで、他方の導電形の拡散領域を、少
なくとも1組選択的に制御して拡散形成させ、か
つこれらの拡散領域間に電圧を印加した状態で、
前記半導体基板の裏面側より導電性のあるエツチ
ング液でエツチングし、エツチングの進行途上で
の前記各拡散領域の露出に伴なう、これらの各領
域間の通電検出により、エツチングの状態を確認
して、所定厚さのダイヤフラムを得るようにした
ことを特徴とする半導体ダイヤフラムの製造方
法。
1 A semiconductor substrate of one conductivity type with a gauge resistor formed on the surface side, and a part of this semiconductor substrate from the surface side with a diffusion depth equal to the thickness of the diaphragm to be obtained, and a conductivity type of the other conductivity type formed on the surface side. selectively controlling and forming at least one set of diffusion regions, and applying a voltage between these diffusion regions,
Etching is performed from the back side of the semiconductor substrate using a conductive etching solution, and as each of the diffusion regions is exposed during etching, the state of etching is confirmed by detecting current flow between these regions. A method for manufacturing a semiconductor diaphragm, characterized in that a diaphragm having a predetermined thickness is obtained by:
JP16601479A 1979-12-19 1979-12-19 Manufacture of semiconductor diaphragm Granted JPS5688372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16601479A JPS5688372A (en) 1979-12-19 1979-12-19 Manufacture of semiconductor diaphragm

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16601479A JPS5688372A (en) 1979-12-19 1979-12-19 Manufacture of semiconductor diaphragm

Publications (2)

Publication Number Publication Date
JPS5688372A JPS5688372A (en) 1981-07-17
JPS6154268B2 true JPS6154268B2 (en) 1986-11-21

Family

ID=15823297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16601479A Granted JPS5688372A (en) 1979-12-19 1979-12-19 Manufacture of semiconductor diaphragm

Country Status (1)

Country Link
JP (1) JPS5688372A (en)

Also Published As

Publication number Publication date
JPS5688372A (en) 1981-07-17

Similar Documents

Publication Publication Date Title
JPS6197572A (en) Manufacture of semiconductor acceleration sensor
US5445991A (en) Method for fabricating a semiconductor device using a porous silicon region
JP3151816B2 (en) Etching method
JPH0527970B2 (en)
US3912563A (en) Method of making semiconductor piezoresistive strain transducer
JPS6154268B2 (en)
JP3508547B2 (en) Si wafer etching method
JP2000124465A (en) Manufacture of semiconductor dynamical amount sensor
JPS63308390A (en) Manufacture of semiconductor pressure sensor
JPS5913377A (en) Formation of pressure receiving diaphragm of semiconductor pressure converting element
JPH0527971B2 (en)
JP3127448B2 (en) Etching control method
JPS62172731A (en) Etching method
JPS6097676A (en) Semiconductor pressure sensor and manufacture thereof
JPH0230188A (en) Manufacture of semiconductor pressure sensor
JPS62183189A (en) Manufacture of semiconductor pressure transducer
JPS63292071A (en) Manufacture of semiconductor acceleration sensor
JPH0645617A (en) Manufacture of single-crystal thin-film member
JPS6356962A (en) Manufacture of semiconductor pressure transducer
JPH06104244A (en) Manufacture of semiconductor device
JPS62266876A (en) Semiconductor pressure sensor
JPS60154575A (en) Manufacture of semiconductor pressure detecting element
JP3361553B2 (en) Method for manufacturing semiconductor device
JPS60211945A (en) Method for formation of thin film
JP3531519B2 (en) Silicon wafer etching method