JPS6153935U - - Google Patents
Info
- Publication number
- JPS6153935U JPS6153935U JP13891684U JP13891684U JPS6153935U JP S6153935 U JPS6153935 U JP S6153935U JP 13891684 U JP13891684 U JP 13891684U JP 13891684 U JP13891684 U JP 13891684U JP S6153935 U JPS6153935 U JP S6153935U
- Authority
- JP
- Japan
- Prior art keywords
- board
- microwave
- integrated circuit
- gold
- electronic components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Multi-Conductor Connections (AREA)
- Wire Bonding (AREA)
Description
第1図は従来のマイクロ波集積回路の外観図、
第2図はこの考案の一実施例によるマイクロ波集
積回路の外観図である。
1…基板、2…導体パターン、3…マイクロ波
トランジスタ、4…キヤリア、5…筐体、6…同
軸コネクタ、7…多極コネクタ、8…金ワイヤ。
なお、図中、同一符号は同一、又は相当部分を示
す。
Figure 1 is an external view of a conventional microwave integrated circuit.
FIG. 2 is an external view of a microwave integrated circuit according to an embodiment of this invention. DESCRIPTION OF SYMBOLS 1... Board, 2... Conductor pattern, 3... Microwave transistor, 4... Carrier, 5... Housing, 6... Coaxial connector, 7... Multipolar connector, 8... Gold wire.
In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
マイクロ波集積回路において、その外部コネクタ
を介して上記基板に内部接続される基板引出しリ
ードを金ワイヤあるいは金リボンで形成したこと
を特徴とするマイクロ波集積回路。 A microwave integrated circuit incorporating a microwave board on which electronic components are mounted, characterized in that a board lead that is internally connected to the board via an external connector is formed of gold wire or gold ribbon. circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13891684U JPH0351900Y2 (en) | 1984-09-13 | 1984-09-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13891684U JPH0351900Y2 (en) | 1984-09-13 | 1984-09-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6153935U true JPS6153935U (en) | 1986-04-11 |
JPH0351900Y2 JPH0351900Y2 (en) | 1991-11-08 |
Family
ID=30697307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13891684U Expired JPH0351900Y2 (en) | 1984-09-13 | 1984-09-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0351900Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6428634U (en) * | 1987-08-13 | 1989-02-20 |
-
1984
- 1984-09-13 JP JP13891684U patent/JPH0351900Y2/ja not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6428634U (en) * | 1987-08-13 | 1989-02-20 |
Also Published As
Publication number | Publication date |
---|---|
JPH0351900Y2 (en) | 1991-11-08 |