JPS6153736A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS6153736A
JPS6153736A JP17547584A JP17547584A JPS6153736A JP S6153736 A JPS6153736 A JP S6153736A JP 17547584 A JP17547584 A JP 17547584A JP 17547584 A JP17547584 A JP 17547584A JP S6153736 A JPS6153736 A JP S6153736A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
semiconductor element
plating
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17547584A
Other languages
Japanese (ja)
Inventor
Noboru Deguchi
出口　登
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17547584A priority Critical patent/JPS6153736A/en
Publication of JPS6153736A publication Critical patent/JPS6153736A/en
Pending legal-status Critical Current

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Die Bonding (AREA)

Abstract

PURPOSE:To eliminate increase of resistance by high temperature shelf test and improve reliability of semiconductor device by directly forming a gold-plated layer on a metallized layer of insulated substrate providing a semiconductor element and also forming an Ni-plated layer on the lead wire. CONSTITUTION:A metallized layer 207 such as W, Mo, etc. is formed on an insulated substrate 202 such as alumina, etc. A metal lead 210 is brazed by Ag-Cu through these layers 207, 209. A semiconductor element 201 is slid, under the condition that AuSb or Au segment is heated at about 400 deg.C, on the layer 209 on the substrate 202 and the Au-Si alloy 203 is formed and cooled and then fixed. Moreover, alumina or saphire cap is adhered to the element 201 with Ag-Sn alloy and these are hermetically sealed. An Ni-plated layer 205 is formed so that the Au plating 204 becomes the base plate to the area exposed to the open air such as metal lead 210. Increase of resistance by high temperature shelf test is eliminated and reliability of semiconductor device can be improved.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は衛星搭載用あるｂは、海底中継器用等の高信頼
度が要求される半導体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a semiconductor device for use in a satellite, and also for use in a submarine repeater, etc., which requires high reliability.

（従来の技術） 従来、＃星搭載用あるｂは海底中継器用等の高信頼度牛
導体装置とじてにアルミナ等のセラミックから成る絶縁
基本に素子を固着し、セラミ、り板あるいはサファイア
板のキャップで内部を気密封止する構造の半導体装置が
一般的ｖＣ１史用されている。また絶縁凸体にに素子の
電極？外部に取りｔ５−′ｒｆｃめの並用リードが取υ
付けらｉしているＣとも一般的である。絶縁基本の半導
体素子固着部に。(Prior technology) Conventionally, the #star-mounted type B is a high-reliability conductor device for submarine repeaters, etc., in which the elements are fixed to an insulating base made of ceramic such as alumina, and the elements are fixed to an insulating base made of ceramic such as alumina. A semiconductor device having a structure in which the inside is hermetically sealed with a cap is generally used in vC1 history. Also, is the electrode of the element on the insulating convex body? A general purpose lead of t5-'rfc is attached to the outside.
It is also common to have C attached to it. For semiconductor element fixing parts with basic insulation.

Ｗ、Ｍ。またに、　Ｍｏ−Ｍｎ等の高融点合価による金
属化層上に、下からＮｉメッキ層及び九メッキ層が菟気
メッキ法等により形成さｉ′シている。半導体素子の固
着はＡｕ１ＡｕＳｂまたはＡ、Ｓｉ等の金槁ソルダーに
エフ行なわれるが、溶融固化後のソルダ一層はシリコン
半導体素子が１部溶融反応に関与するのでＡｕ−８ｉ共
晶の組成金星している。このようＶｒ−構成された半導
体装置全２００　’Ｑあるいは２５０’（！の高温放置
試験？行なった所、半導体装置の熱抵抗が試験前に比較
して著しく増大することを我々は経験した。熱抵抗不良
品を解析し之結果、絶縁基体のＮｉメ、キ層とＡｕ−８
ｉ　ソルダ層間に異層の生成が認められ、異層生成部よ
り半導体素子がはく離していること全確認した。また異
層はＮ、とＳｉ　　の金属間化合物であフ、高温放置の
温度が高いほどまた時間が長いほど顕著であることがわ
かった。し友がって従来の半導体装置の構成では高信頼
度半導体装置としては、使用できず高温放置試験後にも
熱抵抗の増大しない構成が望まれた。W,M. Further, a Ni plating layer and a nine plating layer are formed from the bottom on the metallized layer made of a high melting point compound such as Mo--Mn by a wafer plating method or the like. Semiconductor elements are fixed using gold-plated solder such as Au1AuSb or A, Si, etc., but after melting and solidifying, the solder layer has a composition of Au-8i eutectic because a part of the silicon semiconductor element participates in the melting reaction. There is. When we conducted high-temperature storage tests on all 200'Q or 250' (!) semiconductor devices with this Vr-configuration, we experienced that the thermal resistance of the semiconductor devices significantly increased compared to before the test. As a result of analyzing defective resistor products, it was found that the Ni layer and the Au-8 layer of the insulating substrate were
i It was confirmed that a different layer was formed between the solder layers, and that the semiconductor element was peeled off from the part where the different layer was formed. It was also found that the different layer is an intermetallic compound of N and Si, and the higher the temperature and the longer the time of high-temperature storage, the more pronounced it becomes. Therefore, conventional semiconductor device configurations cannot be used as highly reliable semiconductor devices, and a configuration that does not increase thermal resistance even after high-temperature storage tests has been desired.

（発明が解決しようとする問題点） 本発明の目的は、上記の欠点を除去し、高温放置試験に
おいて金属間化合物の生成による熱抵抗の増大が発生し
ない半導体装置を提供することにある。(Problems to be Solved by the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor device in which an increase in thermal resistance due to the formation of intermetallic compounds does not occur in a high-temperature storage test.

（問題点全解決する定めの手段） 本発明の半導体装置は、絶縁基本の半導体素子固層部金
属化層上にＮｉメッキをまったく介せず。(Determined Means to Solve All Problems) The semiconductor device of the present invention does not require any Ni plating on the metallized layer of the solid layer portion of the semiconductor element, which is based on insulation.

＠接札メッキ層金施し、Ａｕメッキ層上に、半導体素子
１Ａｕ−８Ｕ合金に固着した購成金採用するものである
。また半導体装置の外気露出部（例えば金属リード部）
には、耐熱曲・耐蝕住金、保証するためＮｉメッキ層ヲ
九メ、キ層の下地として介してＩＡる。＠A soldering gold plated layer is applied, and a purchased gold bonded to the semiconductor element 1Au-8U alloy is applied on the Au plating layer. Also, parts of semiconductor devices exposed to the outside air (for example, metal lead parts)
In order to ensure heat resistance and corrosion resistance, a Ni plating layer is used as the base layer for the IA layer.

（作用） この二うに構成した半導体素子であれば、素子の固着部
にはＮｉがまったく存在しないので、前記のＮ、−８，
化合物を形成せず、し念がってはく離ＶＣよる熱抵抗増
大が全く生じない。(Function) In the semiconductor device configured as described above, there is no Ni at all in the fixed portion of the device, so the above-mentioned N, -8,
No compounds are formed, and no increase in thermal resistance occurs due to peeled VC.

（実施例） 次に本発明の実施例を図面音用いて説明する。(Example) Next, embodiments of the present invention will be described with reference to the drawings.

第２図は従来の半導体装置の断面図である。アルミナ等
の絶縁基本１０にはＷ−Ｍｏ等の金属による金属化層１
０７が形成され、金属化層１０７にはＮ・　メッキ層１
０６が施されている。さらに絶縁基本１０２には、金属
化層１０７を介して金属リード１１０がＡｇ−Ｃｕロウ
１０８によりロウ付けされｔ後、最終的にＮｉメ、キ層
１０４及び金メッキ層１０３が施される。FIG. 2 is a sectional view of a conventional semiconductor device. A metallized layer 1 made of metal such as W-Mo is used for insulation basic 10 such as alumina.
07 is formed, and the metallized layer 107 has an N-plated layer 1.
06 is applied. Further, a metal lead 110 is soldered to the insulating base 102 via a metallization layer 107 using an Ag-Cu solder 108, and then a Ni metal layer 104 and a gold plating layer 103 are finally applied.

半導体素子１０１Ｕ、Ａｕ−８ｂ、Ａｕ等の小片を介し
、約４００°ＯＶｃ刀口熱され友状態で摺動され。The semiconductor element 101U is heated to approximately 400° OVc through small pieces of Au-8b, Au, etc. and is slid in a state of contact.

Ａ、−３Ｕ合金１０３を形成し冷却固着される。さらに
半導体素子１０１はアルミナ、あるいはサファイアキャ
ップｋｉ縁基体１０２にＡｕ−８ｎ合金で封Ｎ″ｒるこ
とにより気密封止されている。A, -3U alloy 103 is formed and solidified by cooling. Further, the semiconductor element 101 is hermetically sealed by sealing the alumina or sapphire cap edge base 102 with an Au-8n alloy.

このような構造の牛導体装置全その信頼度を確認するた
めの加速試験のひとつとして筒温放置試験金行うと、試
験後にＡｕ−８Ｕ合金層１０３とＮｉメッキ層１０４の
界面では＜　ＲＬが生じ、結果として装置の熱抵抗が著
しく増大するという欠点がある。この現尿は、Ｎｉメッ
キの熱放置条件によって、その生成速度が異なるが２０
０”０１０００Ｈｒの高温放置試験後には、はぼ全数が
劣化することがわかっている。しんがりて従来の半導体
装置の構成では、衛星搭載用まｆｃは海底中継器用の高
信頼度が要求される半導体装置として使用することがで
きなかっｔｏ 第１図は本発明の一実施例の断面図である。アルミナ等
の絶縁基本２０２に［Ｗ−Ｍｏ等の金属による金属化層
２（１７が形成されている。金属化層２０７　ｉｃはＮ
ｉメッキ金介することなしに直接Ａｕメッキ層２０９が
施される。金属リード２１０は該金属化層２０７及びＡ
ｕメッキ層２０９を介して、Ａｇ−Ｃｕロー付けされる
。半導体素子２０１は絶縁基本２０２上のＡｕメ、キ層
２０９上に札ＳｂまたはＡｕ小片金介して約４００°０
に加熱された状態で摺動され、Ａ、−８ｉ合金２０３全
形成し冷却・固着される。さらに半導体素子２０１にア
ルミナあるいはサファイアキャップｔ−Ａｕ−８ｎ合金
で封着することにより気密封止される。金層リード２１
０など、外気に露出する部分には、耐食性および耐熱性
を良好なものにせしめるため、Ｎｉメ、　キ２０５　ｅ
　Ａｕメ、キ２０４の下地として介している。外気露出
部のＮ、メッキ２０４及びＡｕ　　メッキ２０５はキャ
ップ封止した後１通常の電気メツキ法により施しても工
いし、あるいは。When a cylinder temperature exposure test was performed as one of the accelerated tests to confirm the reliability of the entire conductor device having such a structure, < RL was generated at the interface between the Au-8U alloy layer 103 and the Ni plating layer 104 after the test. , which has the disadvantage that the thermal resistance of the device increases significantly as a result. The rate of generation of this liquid urine varies depending on the heating conditions of the Ni plating, but it is
It is known that almost all devices deteriorate after a high temperature storage test of 0.01000 hours.In the conventional semiconductor device configuration, high reliability for satellite-mounted and submarine repeaters is required. Figure 1 is a cross-sectional view of one embodiment of the present invention.A metallized layer 2 (17) made of a metal such as W-Mo is formed on an insulating base 202 such as alumina. The metallization layer 207 ic is N
An Au plating layer 209 is applied directly without intervening i-plated gold. Metal leads 210 are connected to the metallization layer 207 and A
Ag-Cu is brazed through the U plating layer 209. The semiconductor element 201 is made of an Au layer on the insulating base 202, and a plate Sb or Au small piece is placed on the insulation layer 209 at about 400°0.
The A, -8i alloy 203 is completely formed, cooled and fixed. Furthermore, the semiconductor element 201 is hermetically sealed by sealing it with an alumina or sapphire cap t-Au-8n alloy. gold layer lead 21
Parts exposed to the outside air, such as 205 e
It is used as a base for Au metal and metal 204. The N plating 204 and the Au plating 205 on the parts exposed to the outside air can be applied by a normal electroplating method after the cap is sealed, or alternatively, the N plating 204 and the Au plating 205 can be applied by a conventional electroplating method.

半導体素子の固着前に固着部のみをマスキングして行な
ってもよい。The fixing may be carried out by masking only the fixing portion before fixing the semiconductor element.

このように形成した半導体装置であれば、半導体素子固
１ｅＡｕ−８ｉ合金で行なっても、ＮｉがイＩ在しない
次め、高温放置試験による半導体素子のはく離が生じな
い優れた高信頼度を有する半纏体装置が得られる。筐た
外気露出部は、Ｎｉ　メッキとＡｕ　メッキの２層構造
となっており、従来例と同様の耐熱性・討食性を有して
おり、高信頼度半導体装置として何ら不都合は生じない
。A semiconductor device formed in this way has excellent high reliability, even if the semiconductor element is made of a 1eAu-8i alloy, since no Ni is present, and the semiconductor element does not peel off during high-temperature storage tests. A semi-integrated device is obtained. The part of the casing exposed to the outside air has a two-layer structure of Ni plating and Au plating, and has the same heat resistance and corrosion resistance as the conventional example, and does not cause any problems as a highly reliable semiconductor device.

（発明の効果） 以上、述べｆ′Ｃ工うに本発明によれば、高温放置試験
による熱抵抗増大のない高信頼度を有する半導体装置が
得られるので、その効果は大きい。(Effects of the Invention) As described above, according to the present invention, a semiconductor device having high reliability without an increase in thermal resistance due to a high temperature storage test can be obtained, so the effect is significant.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例による半導体装置の断面図、
第２図に従来の半導体装置の断面図である。 １０１．２０１・・・・・・半導体素子、１０２，２０
２・・・・絶は基体、１０３，２０３・・・・・・Ａｕ
−８１合金。 １０４．２０４，２０９−−−−・−Ａｕメッキ層、１
０５゜１０６．２０５・・・・・・Ｎｉメッキ層、１０
７，２０７・・・・・金属化層（Ｗ、Ｍｏ）、１０８，
２０８・・・・・・＼、−、’：　／ 千　２　図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a sectional view of a conventional semiconductor device. 101.201...Semiconductor element, 102,20
2...absolutely is the base, 103,203...Au
-81 alloy. 104.204,209-----Au plating layer, 1
05゜106.205...Ni plating layer, 10
7,207...Metalized layer (W, Mo), 108,
208...\,-,': / 1,000 2 figures

Claims (1)

【特許請求の範囲】[Claims] 半導体素子がＡｕＳｉ合金により絶縁基体の金属化層上
に載置され、かつ該絶縁基本には、金属リードが取り付
けられてなる半導体装置において、半導体素子が載置さ
れる絶縁基体の金属化層上には、直接金メッキ層が形成
されており、他方外部リード上にはＮｉメッキ層が形成
されていることを特徴とする半導体装置。In a semiconductor device in which a semiconductor element is placed on a metallized layer of an insulating substrate made of an AuSi alloy, and a metal lead is attached to the insulating base, the semiconductor element is placed on a metallized layer of an insulating substrate on which the semiconductor element is placed. A semiconductor device characterized in that a gold plating layer is directly formed on the external leads, and a Ni plating layer is formed on the other external leads.
JP17547584A 1984-08-23 1984-08-23 Semiconductor device Pending JPS6153736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17547584A JPS6153736A (en) 1984-08-23 1984-08-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17547584A JPS6153736A (en) 1984-08-23 1984-08-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6153736A true JPS6153736A (en) 1986-03-17

Family

ID=15996704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17547584A Pending JPS6153736A (en) 1984-08-23 1984-08-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6153736A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009008747A (en) * 2007-06-26 2009-01-15 Tokai Rika Co Ltd Electrochromic mirror
JP2009031731A (en) * 2007-06-26 2009-02-12 Tokai Rika Co Ltd Electrochromic mirror

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009008747A (en) * 2007-06-26 2009-01-15 Tokai Rika Co Ltd Electrochromic mirror
JP2009031731A (en) * 2007-06-26 2009-02-12 Tokai Rika Co Ltd Electrochromic mirror

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