JPS6066842A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6066842A
JPS6066842A JP17580883A JP17580883A JPS6066842A JP S6066842 A JPS6066842 A JP S6066842A JP 17580883 A JP17580883 A JP 17580883A JP 17580883 A JP17580883 A JP 17580883A JP S6066842 A JPS6066842 A JP S6066842A
Authority
JP
Japan
Prior art keywords
chip
ceramic
fixed
piers
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17580883A
Other languages
Japanese (ja)
Inventor
Kiyoshi Kuwabara
清 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17580883A priority Critical patent/JPS6066842A/en
Publication of JPS6066842A publication Critical patent/JPS6066842A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3733Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To easily contain a carrier having good heat dissipation when an IC is fixed to the central portion of a ceramic chip carrier to form a semiconductor device, by providing piers having good heat conductivity in the IC chip carrying section and by providing a metallizing layer on the lower face thereof to be connected to the external cooling means. CONSTITUTION:When a semiconductor chip 3 is fixed on the central surface of a ceramic substrate 1, a multiplicity of piers having a high heat flow density and a low thermal resistance are implanted vertically, while being disposed parallel to one another. A metallizing layer 15 is adhered to the lower faces of these piers for covering the same, and a cooling core 10 having cooling fins 11 is fixed to the layer 15. After a chip 3 is fixed on the carrying section in a cavity 2, the electrode wirings of the chip 3 are connected to the pads 4, external terminals 5, connection terminals 6 or the like with the use of bonding wires 7 as usual, and the chip 3, the pad 4 and so on are covered with a cover 8.

Description

【発明の詳細な説明】 fat 発明の挾1]・1分9!を 本発明は半導体装置に係り、特に収納される半導体装積
回路素子の冷却手段として、高熱伝導率のビアを備えた
基板を有する半導体装置に関する。
[Detailed description of the invention] fat Invention 1]・1 minute 9! The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a substrate provided with a via having high thermal conductivity as a cooling means for a semiconductor integrated circuit element housed therein.

(El)技術の背景 逐年、電了槻器の処理能力が増大するのに伴い半導体集
Ki1回路素子(以F’ICと称しLSIを含む)自体
の発F;ら(1,1叱G、1」二yl!の一途を辿って
いる。i;I記のIc素子の接合温度が上がると故1(
苧率かIll <なシ)。
(El) Technology background As the processing power of electronic devices increases year by year, the semiconductor integrated circuit element (hereinafter referred to as F'IC and includes LSI) itself is developed. 1" 2yl!
The rate of ramie is Ill <nashi).

また動作中に接合ン品度がある幅量1−に変動すると該
素子の動作点が変化して出力レベルの変動がイ1−しる
ので、当該電子回路の誤動作を招く恐1′1.がある等
、電子機器の安定動作をrlT〔保′4゛る観点からも
Furthermore, if the bonding quality fluctuates by a certain amount during operation, the operating point of the element changes and the output level fluctuates, which may lead to malfunction of the electronic circuit. From the perspective of maintaining the stable operation of electronic equipment, such as:

半導体素子の冷却は緊急な問題と);(っ“(いる。Cooling of semiconductor devices is an urgent issue.

(c+ 従来技術と問題点 通常のIcのセラミソクチ、ブキャリアはり−I一端子
を有する従来のものも、リ−1” 61:l J″のな
いリードレスチップギヤリアにしても、第1図Gこ小ず
ように、半導体集積回路素子、所謂半導体千ノブはセラ
ミックの占(1反」二にjh栽され(いる。
(c+ Conventional technology and problems) Even if the conventional type with a normal Ic ceramic socket, butcher beam, and I terminal, or the leadless chip gear without lead 1" 61:l J", Fig. 1G Semiconductor integrated circuit elements, the so-called semiconductors, are being cultivated in every ceramic industry.

従来例としてり−I、−レスチノフーーヤリアを第1図
の斜視図および第2図のlli面図に示′4−。セツミ
ック基板1上の空間部のキャビティ2の底面に。
As an example of the prior art, a restino-furyer is shown in a perspective view in FIG. 1 and a side view in FIG. 2. At the bottom of the cavity 2 in the space above the static substrate 1.

メタライジングで形成された金属膜に金メッキを施した
半導体チップ接続部が設りられ、その十に。
A gold-plated semiconductor chip connection part is provided on the metal film formed by metallization.

半導体チップ3が半田4qり等のツノlJ、で固定され
The semiconductor chip 3 is fixed with solder 4q or other horns lJ.

その周辺のキャビティ2の底面1.X4.’1.’ 、
 4電惺4A利の厚膜で形成されたボンディングパ、1
4が配設されていて1.ノタフイ/ング法でチップ基板
1の側面を経て裏面に達する外部接続端子5に連結して
いる。その先端部はりフロー法でプリン1一基板(図示
セず)に実装するのに便利なように金メンキされ゛(I
u l;、rli Eiを構成している。半導体装ツブ
3とポンディングバノト4とは細い金線のボンディング
ヮイート7でボンディングされている。蓋部8は半導体
装ノブ3を密封するためのセラミ・ックイにである。
The bottom surface of the cavity 2 around it 1. X4. '1. ',
4 Bonding pad made of thick film with 4A characteristics, 1
4 are arranged and 1. It is connected to external connection terminals 5 which reach the back surface of the chip substrate 1 through the side surface thereof using a notafing method. Its tip is gold-plated to make it convenient for mounting on a printed circuit board (not shown) using the beam flow method.
ul;, rli Ei. The semiconductor chip 3 and the bonding plate 4 are bonded with a bonding piece 7 made of a thin gold wire. The lid part 8 is a ceramic container for sealing the semiconductor device knob 3.

このようなセラミック・チップキャリアをプリン1一基
板(図ホーロず)に搭載すると、前記半導体J−ノゾ3
で発止した!:J)はセラミック基板1を経由に(メ゛
ハ伝導(移動し、接続部6とプリント詰1にとの18続
用の)1i田(zIすIef (図示ゼず)を経てプリ
ン1一基板の低11’lA i’i1+に休し、そこか
らh交熱される。勿論むラミック・チップキャリア自体
の表面がらも。
When such a ceramic chip carrier is mounted on the printed circuit board 1 (not shown), the semiconductor J-no.
It started! :J) is connected to the pudding 1 through the ceramic substrate 1 (for 18 connections between the connection part 6 and the print 1) via the ceramic substrate 1 (not shown). It rests in the lower 11'lA i'i1+ of the substrate, and heat is exchanged therefrom, including, of course, the surface of the ramic chip carrier itself.

1、=述の熱伝導の径1洛の表面がらも、熱放射や空気
流への熱伝達で放熱される。さらに上述のh9.かシを
91果的にするノこめに、各種のヒートシンクを設けて
自然文j流や強;1.す気流冷却、あるいはり41制液
冷却鮒等のあらゆる冷却手段が講じら4N、−Cいる。
1. Even from the surface of the heat conduction diameter 1, as mentioned above, heat is radiated through heat radiation and heat transfer to the air flow. Furthermore, the above-mentioned h9. Various types of heat sinks are installed to make the oak 91 more effective; 1. All kinds of cooling means such as airflow cooling or 41 liquid cooling method are used.

然し、もっとも肝要なのはjJ5源である半導体チップ
3から周囲への熱流密度の高い敢タハ路の熱11(抗を
低く保つことである。そのためセラミ、り基板1の半導
体装ツブ3搭載部分のよ’I下の)、(板裏面に第3図
に示すように接着用のメタライス層1)を形成し、これ
に冷却フィンIIを備え4こ冷却、TI −j’ 10
(通常、銅かアルミニウム!!i!りを半1]j ((
1り等て接着したり、第4図に示すように、↑Jjlの
冷却二ノアIOをセラミック基板1を貫通してセラミ、
り・チップキャリアのキャビティ2内に+:+を人し、
その先”’!t、lに半導体チップ3を搭載する構迅が
試められ′(いる。(特開昭55−165657 ) 第4図において、13はセラミック基11i 1と銅製
の冷却コア1oとの間の熱膨張係数の差による5;ノシ
応力を回避するだめのコバール(鉄・ニッケル・Jノハ
ルト合金)製の中継部品である。
However, the most important thing is to keep the heat 11 (resistance) low in the heat path where the heat flow from the semiconductor chip 3, which is the source of jJ5, to the surroundings is high. TI-j' 10
(Usually copper or aluminum!!
1, etc., or as shown in FIG.
・Insert +:+ into cavity 2 of the chip carrier,
Beyond that, an attempt was made to mount a semiconductor chip 3 on the semiconductor chip 3. 5 due to the difference in thermal expansion coefficient between

冷却すべき半導体装ノブ3に直接にin+熱伝導率の冷
却ブロックを具備した点で、第4図に示したものは第3
図に示した例、J−リ1lljい放f゛引ηを(Aiえ
Cはいるか5図から明らかなように、構造が複雑でil
i、<、二+スト1)31、ひ取り扱い上の欠点があっ
た。
The one shown in FIG. 4 is different from the one shown in FIG.
In the example shown in the figure, the structure is complex and the
i, <, 2 + strike 1) 31, had a drawback in handling.

(+Il 発明の目的 本発明は前述の点に鑑みなされたもので、従来のセラミ
、り・チップキャリアよりも放熱性が優れ、かつ筒車で
軽い構造のセラミック・千ノブキャリアを提供しようと
するものである。
(+Il Purpose of the Invention The present invention has been made in view of the above-mentioned points, and aims to provide a ceramic thousand-knob carrier that has better heat dissipation than conventional ceramic chip carriers and has a lightweight hour wheel structure. It is something.

((41発明の構成 上記の発明の目的は、セラミック・チップキャリアの1
118中火部に半導体集積回路素子を収納してなる半導
体装置において、該セラミック・チップキャリアを構成
′Jるセラミ、クチツブ基板の1111記半導体集U1
回路素子を搭載する部分に熱伝導性の良いビアを設りる
と共に、外部冷却手段と接続されるメタライジング崩を
形成したことを特徴とする半I〃体装:;す゛を使用す
ることで、容易に達成される。
((41 Constitution of the Invention) The object of the above invention is to
118 In a semiconductor device comprising a semiconductor integrated circuit element housed in a medium heat section, the semiconductor assembly U1 of 1111 is a ceramic, ceramic substrate constituting the ceramic chip carrier.
By using a semi-I housing, which is characterized by providing vias with good thermal conductivity in the part where the circuit elements are mounted, and forming a metallized break that is connected to the external cooling means. , easily achieved.

m 発明の′JJ施例 流側明の詳細な説明する前に第1図3第2図に小したり
一ルス千ノブキャリアの外部接続端子5の代わりに、ビ
アをイjするものがあることを述べよう。実装密度が−
・Ii +rli <な−2てくると、L!セラミック
チップキャリアの端子数も増加し、そのピッチも小さく
なって来るので、外部接続i’+(i’+ ’j’5で
は対応しきれなくなり、ビアが採用さj′?、ている。
Before we give a detailed explanation of the current implementation of the invention, there is one in which a via is provided in place of the external connection terminal 5 of the small or one-knob carrier as shown in Figure 1, Figure 3, and Figure 2. Let me tell you something. Packing density is -
・When Ii +rli <na-2 comes, L! As the number of terminals on ceramic chip carriers increases and the pitch between them becomes smaller, external connections i'+(i'+'j'5) are no longer sufficient, and vias are being adopted.

図では示さないが、ビアとはセ’+”: ’/り基1綬
1のキャビティ2側から基板のセラミ、り部分を貫いて
基板1の裏面に達している導tIl性の物I′fで構成
された端子である。セラミック粉末にモリブデンやタン
グステン等のセラミック4,111σ薯;ハ膨張係数に
近くかつ高融点の金属材料を混合したものを、セラミッ
ク基板1の4′5)未整形時に多数の11扶をなして整
形しておき、セラミックと同時に焼成して形成する。本
発明はこの構造を利用したものである。
Although not shown in the figure, a via is a conductive material I' that extends from the cavity 2 side of the substrate 1 through the ceramic layer of the substrate and reaches the back surface of the substrate 1. This is a terminal made of ceramic powder mixed with a metal material having a high melting point and an expansion coefficient close to the ceramic powder such as molybdenum or tungsten. Sometimes, it is shaped into a large number of 11 pieces and fired at the same time as the ceramic.The present invention utilizes this structure.

以下本発明の実施例につき図面を参jj4j して説明
する。第5図および第6図44本発明に基−づ<゛1′
導体集積回路素子のセラミック・千ノブキャリアの一実
施例の構造を示す断面図と裏面図である。
Embodiments of the present invention will be described below with reference to the drawings. Figures 5 and 6 44 Based on the present invention <゛1'
FIG. 2 is a cross-sectional view and a back view showing the structure of an embodiment of a ceramic carrier for a conductive integrated circuit element.

第5図の断面図で示すように9本実施例のセラミック基
板1の21′導体チップ3の搭載位置に多数のビア14
を形成する。このビア14は通電のチップキャリアのビ
アとは異なり、熱伝導により半導体ナツプ3のh9.敗
する熱を外部に放熱するのが目的であるので、極力ビア
14自体の熱伝導率を1ffi <とるために、含イj
する金属成分を高率にしである。
As shown in the cross-sectional view of FIG.
form. This via 14 is different from the via of a current-carrying chip carrier, and the h9. Since the purpose is to dissipate the lost heat to the outside, in order to make the thermal conductivity of the via 14 itself as low as 1ffi, it is necessary to include
It contains a high proportion of metal components.

またその個数も出来るだけ多くして密度を上げることが
重要である。総てのビア14はセラミック基板Iの裏面
においてメタライジング層よりなる接続部15に接続し
ている。接続部15は各ビア14をまとめて、冷却フィ
ン11の冷却コア10へ接着するために設りられたもの
で、半導体チップ3で発生した熱は主とし″CCテア4
を経て冷却フィン11に達し。
It is also important to increase the number of particles as much as possible to increase the density. All the vias 14 are connected to a connection part 15 made of a metallized layer on the back surface of the ceramic substrate I. The connecting portion 15 is provided to bond the vias 14 together to the cooling core 10 of the cooling fin 11, and the heat generated in the semiconductor chip 3 is mainly transferred to the CC tear 4.
The cooling fins 11 are reached through the cooling fins 11.

ここから外9Bへ放熱される。Heat is radiated from here to outside 9B.

第6図はビア■4の配設状況を示す裏面図で1分り易い
ようGこ接1)’M r!B l 5を除いて表現しで
ある。
Figure 6 is a back view showing the arrangement of via ■4 for easy understanding. This is the expression except for B l 5.

第7図は冷却フィンを装着した例を示すものである。I
j;j述のように冷却フィン+1を有する冷却コア10
を半田伺iノ法でセラミック基板1の裏面の接り′5部
15に接着する丈でよく、第4図に比して、構造が非常
に簡単かつ堅牢なことが川る。
FIG. 7 shows an example in which cooling fins are installed. I
j; cooling core 10 having cooling fins +1 as described in j;
The length is sufficient to bond it to the joint 15 on the back side of the ceramic substrate 1 using the soldering method, and the structure is much simpler and more robust than that shown in FIG. 4.

なお、第7図に示したセラミック・千ノブ−1’−トリ
アは外部接続端子5を有するり一ルス千ノゾキャリアで
あるが、ビアを有する一f−ノブ4−ヤリアでもよく、
またリード匍1′5子を自゛4るセラミック・チップキ
ャリアにも適用出来ることは自明である。
Note that the ceramic 1000-knob-1'-tria shown in FIG. 7 is a 100-knob carrier having an external connection terminal 5, but it may also be a 1f-knob 4-yaria having a via.
It is also obvious that the lead plate 1'5 can be applied to any ceramic chip carrier.

更に付言すると、第5図に示したビア目群を1トとめて
、セラミックチップ基板Iのキャビティ2側より裏面側
に連続した太い焼結金属層を形成したらより有効である
ことは論をまたないが、実I’′!I。
Additionally, it goes without saying that it would be more effective if the group of via holes shown in FIG. No, but I'm real! I.

」二、前述のタングステンやモリブデン等の金属粉末成
形体とセラミックの粉末成形体との焼成1時の収縮率は
著しく相違するので、実現イ石1J能でij)る。
2. Since the contraction rate of the metal powder molded body of tungsten, molybdenum, etc. mentioned above and the ceramic powder molded body at the time of firing is significantly different, it is difficult to realize it.

依って9本発明においては多数のビアI4の集合体とし
たものである。
Therefore, in the present invention, a large number of vias I4 are assembled.

(g+ 発明の効果 以」二の説明から明らかなように1本発明によるセラミ
ック・千ノブキャリアに21ツ導体隼■責回1/8 J
L:子を搭載すると、該素子に発生ずる多′ハをセラミ
’7り基板等の熱伝導率の低い月1′−1を介するので
なく。
(g+ Effects of the Invention) As is clear from the explanation in Part 2, the ceramic thousand-knob carrier according to the present invention has 21 conductors and 1/8 J
L: When the element is mounted, the polygons generated in the element are not passed through a ceramic substrate or the like having low thermal conductivity.

熱伝導率の、[IIいビア群を介して、直接に発生熱を
り(部に導いて冷却処理出来るので、当該半導体集積回
路素子の(liJJ作安定と品質の向上が可能であるは
かりでなく、さらに1■密度実装を可能にするというリ
ノ果がある。またこの種の構造としては従来の例に比し
て簡単堅牢であり原価を低減出来るという利点もある。
The generated heat can be directly guided and cooled through a group of vias with low thermal conductivity, so it is possible to improve production stability and quality of the semiconductor integrated circuit device. In addition, this type of structure has the advantage of being simpler and more robust than conventional examples, and can reduce cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図と第2図は従来のリードレスチップキャリアの構
造の一例を示す斜視図と断面図、第3図と第4図は従来
のリードレスチップキャリアの冷LI+構造の例を示す
断面図、第5図と第(1図は本発明に基づくセラミック
・チップキャリアの一実施例の構造を〉1<ず断面図と
裏面図1第7図は本発明にノ、(つくセツミック・千ノ
ブキャリアの一実施例にス・1する冷却手段の装着例を
示した断面図である。 図におい′C91はセラミ’7り基板、2はキャビラー
イ、3は一゛1り導体集積回路素子、4ばボンディング
バノ1.5は外111も接続端子、6は接続部、7はポ
ンディンクリイー1・、8はMt’!B、9. 15は
メタライジング層の接続g++、toは冷却コア、11
は冷却フィPン、]3は中紺部、14はビアをそれぞれ
;l<す。 第 114 6 第 3Δ 110 第 2 図 *Os 4 +(1
Figures 1 and 2 are perspective views and cross-sectional views showing an example of the structure of a conventional leadless chip carrier, and Figures 3 and 4 are cross-sectional views showing an example of the cold LI+ structure of a conventional leadless chip carrier. , FIG. 5 and (FIG. 1 shows the structure of an embodiment of the ceramic chip carrier according to the present invention). It is a cross-sectional view showing an example of mounting a cooling means on an embodiment of the carrier. The bonding vane 1.5 is the connection terminal for the outer 111, 6 is the connection part, 7 is the bonding ring 1., 8 is Mt'!B, 9. 15 is the connection g++ of the metallizing layer, and to is the cooling core. , 11
3 is a dark blue part, and 14 is a via, respectively. 114th 6th 3Δ 110th Fig. 2 *Os 4 + (1

Claims (1)

【特許請求の範囲】[Claims] セラミック・千ノフ゛キャリアの略中央部に半導体装(
1゛1回i/&素rを収納してなる半導体装置であっ−
(、該セラミック・チップキャリアを構成するセラミノ
クチノブ基板の111]記半導体集積回路素子を搭載す
る部引にチリシ伝導性の良いビアを設りると共に、外部
冷却手段と接続されるメタライジング層を形成したこと
を特徴とする半導体装置。
A semiconductor device (
1゛It is a semiconductor device that stores i/& element r once.
(111 of the ceramic cutter knob substrate constituting the ceramic chip carrier) A via with good conductivity is provided in the area where the semiconductor integrated circuit element is mounted, and a metallizing layer is formed to be connected to an external cooling means. A semiconductor device characterized by:
JP17580883A 1983-09-22 1983-09-22 Semiconductor device Pending JPS6066842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17580883A JPS6066842A (en) 1983-09-22 1983-09-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17580883A JPS6066842A (en) 1983-09-22 1983-09-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6066842A true JPS6066842A (en) 1985-04-17

Family

ID=16002592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17580883A Pending JPS6066842A (en) 1983-09-22 1983-09-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6066842A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5138439A (en) * 1989-04-04 1992-08-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5721454A (en) * 1995-12-20 1998-02-24 Intel Corporation Integrated circuit package with a plurality of vias that are electrically connected to an internal ground plane and thermally connected to an external heat slug
WO1999049283A1 (en) * 1998-03-23 1999-09-30 Siemens Aktiengesellschaft Support for a temperature-sensitive resistor
US6023098A (en) * 1995-06-29 2000-02-08 Fujitsu Limited Semiconductor device having terminals for heat radiation
EP2071620A1 (en) * 2007-12-12 2009-06-17 Wen-Long Chyn Heat sink having enhanced heat dissipation capacity

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5138439A (en) * 1989-04-04 1992-08-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6023098A (en) * 1995-06-29 2000-02-08 Fujitsu Limited Semiconductor device having terminals for heat radiation
US5721454A (en) * 1995-12-20 1998-02-24 Intel Corporation Integrated circuit package with a plurality of vias that are electrically connected to an internal ground plane and thermally connected to an external heat slug
WO1999049283A1 (en) * 1998-03-23 1999-09-30 Siemens Aktiengesellschaft Support for a temperature-sensitive resistor
EP2071620A1 (en) * 2007-12-12 2009-06-17 Wen-Long Chyn Heat sink having enhanced heat dissipation capacity

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