JPS6152495B2 - - Google Patents
Info
- Publication number
- JPS6152495B2 JPS6152495B2 JP54026473A JP2647379A JPS6152495B2 JP S6152495 B2 JPS6152495 B2 JP S6152495B2 JP 54026473 A JP54026473 A JP 54026473A JP 2647379 A JP2647379 A JP 2647379A JP S6152495 B2 JPS6152495 B2 JP S6152495B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- information
- area
- majority
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Multi Processors (AREA)
- Hardware Redundancy (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2647379A JPS55119753A (en) | 1979-03-07 | 1979-03-07 | Information input method in electronic computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2647379A JPS55119753A (en) | 1979-03-07 | 1979-03-07 | Information input method in electronic computer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55119753A JPS55119753A (en) | 1980-09-13 |
| JPS6152495B2 true JPS6152495B2 (enrdf_load_html_response) | 1986-11-13 |
Family
ID=12194472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2647379A Granted JPS55119753A (en) | 1979-03-07 | 1979-03-07 | Information input method in electronic computer system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55119753A (enrdf_load_html_response) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004105241A1 (ja) | 2003-05-21 | 2004-12-02 | Fujitsu Limited | 多数決論理回路を有するフリップフロップ回路 |
| US10318376B2 (en) * | 2014-06-18 | 2019-06-11 | Hitachi, Ltd. | Integrated circuit and programmable device |
-
1979
- 1979-03-07 JP JP2647379A patent/JPS55119753A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55119753A (en) | 1980-09-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6948010B2 (en) | Method and apparatus for efficiently moving portions of a memory block | |
| EP0306244B1 (en) | Fault tolerant computer system with fault isolation | |
| EP0306252B1 (en) | Fault tolerant computer system input/output interface | |
| US5249187A (en) | Dual rail processors with error checking on I/O reads | |
| US6687851B1 (en) | Method and system for upgrading fault-tolerant systems | |
| US5291605A (en) | Arrangement and a method for handling interrupt requests in a data processing system in a virtual machine mode | |
| US3680052A (en) | Configuration control of data processing system units | |
| CN113064748A (zh) | 进程接替的方法、装置、电子设备及存储介质 | |
| EP0403168B1 (en) | System for checking comparison check function of information processing apparatus | |
| JP3216996B2 (ja) | 二重系電子連動装置 | |
| US4169288A (en) | Redundant memory for point of sale system | |
| JPS6152495B2 (enrdf_load_html_response) | ||
| JP2626127B2 (ja) | 予備系ルート試験方式 | |
| JP3266956B2 (ja) | システム記憶装置 | |
| JPS6218059B2 (enrdf_load_html_response) | ||
| SU1734251A1 (ru) | Двухканальна резервированна вычислительна система | |
| JPS6239792B2 (enrdf_load_html_response) | ||
| JPS63195746A (ja) | ログ処理方式 | |
| US6480945B2 (en) | Method and apparatus for controlling memory access by a plurality of devices | |
| JPS61150041A (ja) | 二重化情報処理システム | |
| JPS6010343B2 (ja) | 情報処理系の制御方式 | |
| SU900278A1 (ru) | Устройство дл управлени дуплексной системой | |
| JPS59123056A (ja) | 冗長機能自動切替システム | |
| JPH0441395Y2 (enrdf_load_html_response) | ||
| JPH0821012B2 (ja) | ダイレクトメモリアクセスの系切替装置 |