JPS6152495B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for inputting information in a computer system configured in multiple ways with at least three computers.

Equipment that requires highly reliable control (for example, traffic lights and point switches in transportation systems, hereinafter referred to as high-reliability equipment) is controlled by synchronized operation of three electronic computers. In a control device that directly controls the output signal using a majority vote signal,
Information such as programs and data for controlling highly reliable equipment may be rewritten.

However, in the past, new information was input to each computer via an operator console to perform the rewriting, which took time.

The present invention focuses on the fact that in a multi-configuration computer system, each computer is provided with a large number of circuits, and the contents of the memory can be modified using a majority signal of the output signals of each computer. An object of the present invention is to provide an information input method that allows information to be rewritten quickly and accurately without using a data transmission channel, a direct memory access channel, or the like.

In the present invention, new information is written in a predetermined area of the memory of a specific computer, and one of the areas corresponding to the area in each memory of other computers is set to a logic signal "1". , the other logic signal is set to "0", and then the above-mentioned new information is written to another computer using the data recovery function in the multiple computer system, thereby achieving the above object.

In other words, a multi-configuration electronic computer system is
In general, it has a data restoration function that matches the output signals of each computer in a majority circuit, writes the majority signal to each memory of each computer, and matches the information in each memory between computers. Accordingly, the present invention writes new information to a predetermined area of the memory of at least one electronic computer, and writes one of the areas corresponding to the area among the memories of even number of electronic computers to a logical signal " 1” to
After setting the other to the logic signal "0", the information in each area is verified by the majority decision circuit, and the majority decision signal is written to the memory having the area set to at least the logic signals "1" and "0". This allows new information to be input to each computer.

In this way, it is not necessary to input new information to each computer via the operator console, so information can be rewritten in a short time, and data recovery function in a multi-configuration computer system is possible. By using
Accurate input can be performed without using a data transmission channel, direct memory access channel, etc., and there is no possibility that the input information will differ between computers.

The majority vote signal may be written only to each area set to logic signals "1" and "0"; however,
It is preferable to write to the area where new information has been written and to the areas set to logic signals "1" and "0" because the data restoration program can be used as is. Further, it is preferable to write in areas other than the above-mentioned areas and compare and check the written information with the new information inputted first, since the reliability will be higher.

At least one computer inputs new information for the first time, but the same number of computers sets specific areas to logic signals "1" and "0". Therefore, the ratio of the number of computers to which new information is input for the first time, the number of computers to which the logic signal is set to "1", and the number of computers to which the logic signal is set to "0" is 1:1:1 if the system is triplex, 1:2:2 or 3:1:1 if the system is quintuple, 1:3:3, 3:2:2 if the system is heptad. , 5:1:1. However, it is preferable to use only one electronic computer to which new information is first input, since the smaller the number of computers, the shorter the time required.

The embodiments shown in the drawings will be described below.

The figure shows high-reliability equipment that is configured to restore information using data bus lines, and equipment that does not require reliable control (for example, data transceivers and guidance displays in transportation systems). This is an example of a multi-configuration electronic computer system that controls multiple devices (hereinafter referred to as general reliability devices). In the figure, 1a, 1b, 1c are electronic computers that are operated synchronously, and the central processing unit 2
a, 2b, 2c, and memories 3a, 3b, 3c,
Majority circuits 4a, 4b, 4c and two types of interface circuits 5a, 5b, 5c, 6a, 6b,
6c, and synchronous logic circuits 7a, 7b, and 7c.

Each memory 3a, 3b, 3c is equipped with a common state memory and constant memory, and the same management program such as a monitor program for operating the corresponding central processing unit in synchronization with the central processing unit of the corresponding central processing unit. The same program for controlling the highly reliable device 8 and various variable constants for the highly reliable device 8 are stored respectively. Further, the memory 3a stores a program and data for controlling the first general reliability device 9a, and the memory 3b stores a program and data for controlling the second general reliability device 9b. 3c stores a program for controlling the operator console 10 such as a teletypewriter, an operation program for the entire system, and the like. The memory 3c further stores a program for monitoring failures of the electronic computers 1a and 1b.

The majority circuits 4a, 4b, 4c are connected to each memory 3.
This is a known circuit that collates the information read from the CPUs 2a, 3b, and 3c by majority vote, and is connected to supply the majority vote signal to the corresponding central processing units 2a, 2b, and 2c. Each majority circuit 4a, 4b, 4c
is used when matching the contents of various registers such as program counters provided in the central processing units 2a, 2b, 2c, and/or the contents of the memories 3a, 3b, 3c (when restoring data).

The interface circuits 5a, 5b, and 5c are connected to a high reliability device 8 via a majority circuit 11 made of a hardwired logic circuit using fail-safe elements. The interface circuit 6a is connected to a first general reliability device 9a, the interface circuit 6b is connected to a second general reliability device 9b, and the interface circuit 6c is connected to a second general reliability device 9b.
is connected to the operator console 10.

The synchronous logic circuits 7a, 7b, 7c are connected to the timer 12.
Based on the constant frequency synchronization signal input from
This is a known circuit that operates a corresponding central processing unit in synchronization with other central processing units, and each time the synchronization signal is input from the timer 12, it interrupts the corresponding central processing unit and also operates each central processing unit. The corresponding central processing unit is made to wait until the corresponding central processing unit becomes able to execute interrupt processing. That is, each synchronization logic circuit 7a, 7b, 7c is set when the synchronization signal 20 is input from the timer 12, and inputs an interrupt signal 21a, 21b, 21c to the corresponding central processing unit, and each central processing unit performs an interrupt. Wait signals 23a, 2 that cause the corresponding central processing unit to wait until outputting the approval signal 22a, 22b, 22c.
3b and 23c, and when each central processing unit becomes able to execute interrupt processing, it is reset by the AND signal of the interrupt approval signal input from each central processing unit, and interrupt processing in the corresponding central processing unit is executed. Allow.

The standby signal is valid only when each central processing unit should be operated synchronously, such as when a program for the highly reliable equipment 8 is to be executed (when the highly reliable equipment is to be controlled), 9a, 9b,
It is invalidated when each program for use and loading is to be executed. Therefore, each central processing unit 2a, 2b, 2c has general reliability equipment 9a, 9
When controlling b, they operate individually.

The majority circuit 11 is a three-way circuit using a parametron etc.
This is a known circuit made fail-safe using value logic elements, and is used to determine the coincidence state of control signals for the highly reliable equipment 8 output by each computer 1a, 1b, 1c for every two computers. Equipped with a judgment circuit. Moreover, the majority circuit 11 is configured to disconnect the failed computer when any of the electronic computers fails and output a signal that matches the output signals of the normally operating computers (match only on the control side). has been done. The output signal of the determination circuit is
In the central processing unit 2c, it is used as a signal to monitor computer failure.

The highly reliable device 8 is, for example, a traffic signal or a switch in a transportation system, the first general reliability device 9a is, for example, a data transmitter/receiver in the transportation system, and the second general reliability device is, for example, a guide display in the transportation system. be able to.

When each central processing unit 2a, 2b, 2c should control the highly reliable device 8, it waits until the corresponding synchronous logic circuit 7a, 7b, 7c is reset, and when it is reset, the contents of the internal register, and the data regarding the management program to the majority decision circuit 4.
a, 4b, and 4c, and after matching between each central processing unit, the program for the highly reliable device 8 is executed synchronously, and the control signal for the highly reliable device 8 is sent to the interface circuit. Output to 5a, 5b, 5c. Furthermore, when the general reliability devices 9a and 9b are to be controlled, the central processing unit 2a executes a program for the general reliability device 9a, and the central processing unit 2d executes a program for the general reliability device 9b, respectively. Then, control signals for the general reliability devices 9a and 9b are individually output to the interface circuits 6a and 6b, and the central processing unit 2c is idling.

Note that the idling time of each central processing unit and the contents of the sequence counter are monitored by a management program. Further, the instruction to switch the program to be executed is given by the management program according to the contents of the sequence counter.

In the above-mentioned device, when changing (or inputting) the program and/or data for the highly reliable equipment 8, use the operator console 10 to input new information into the computer 1c, and send the information transfer command electronically. All you have to do is input it into the calculator 1c. In this way, the computer 1c writes the input new information to a predetermined area (for example, addresses 1000 to 2000) of the memory 3c, and then writes the input new information to the area (1000 to 2000) when the information transfer command is input.
A rewriting command for the area (addresses 1000 to 2000) corresponding to the address) is output to the computers 1a and 1b. When the rewriting command is input to the electronic computers 1a and 1b, one of the computers 1a and 1b sets the area (addresses 1000 to 2000) to a logic signal "1" and the other computer 1b to a logic signal "0". When this set processing is completed, each electronic computer 1a, 1b, 1c outputs the information of the area to the majority circuits 4a, 4b, 4c,
The majority signal is sent to the area (addresses 1000 to 2000)
synchronously execute the data recovery process written to the When the data restoration process is completed, the electronic computer 1c
Information in the area and operator console 1
Compare and check the new information input from 0.
Therefore, the computer 1c stores the new input information in an area other than the area (addresses 1000-2000) (for example, addresses 3000-4000).
If there is no match as a result of the comparison, each computer is caused to execute the above-mentioned processes again.

The above-mentioned rewrite process is executed at any time by monitoring the time when the program completes a predetermined process, the time before outputting a control signal for the highly reliable device 8, etc. using the management program. Alternatively, it may be performed when information is transferred between electronic computers.

The present invention is applicable not only to computer systems that use data bus lines to restore data, but also to electronic computer systems that use specific input/output circuits to restore data, as well as majority circuits. It can be applied to any multi-configuration electronic computer system in which data can be restored using the following methods.

As described above, the present invention eliminates the need to input new information to each computer via the operator console, so that information can be rewritten in a short time. You can also use the data recovery function to
Since the new information and the majority signal of the two types of information set are written, accurate input can be made without the need for special circuits or programs, and there is no risk that the input information will differ between computers. .

[Brief explanation of the drawing]

The figure is a block diagram showing an example of a triple electronic computer system. 1a, 1b, 1c...electronic computer, 2a, 2b,
2c...Central processing unit, 3a, 3b, 3c...Memory, 4a, 4b, 4c...Majority circuit, 5a, 5
b, 5c, 6a, 6b, 6c...interface circuit, 10...operator console.

Claims (1)

[Claims] 1. In a multi-configuration electronic computer system in which information is repaired using a majority circuit,
New information is written in a predetermined area of the memory of at least one computer, one of the areas corresponding to the area of the other computers is set to a logic signal "1", and the other is set to a logic signal "1". After the logic signal is set to "0", information in each area is collated by a majority vote by the plurality of circuits, and the majority decision signal is written into a memory having the area set to at least the logic signals "1" and "0". An information input method in an electronic computer system characterized by: 2. The information input method according to claim 1, wherein the majority signal is written into the area set to at least logic signals "1" and "0". 3. The information input method according to claim 1 or 2, wherein the majority vote signal is written into a corresponding area of each memory of each computer. 4. Claim 1 in which the majority signal is written in the area where new information is first written and in each area set to logic signals "1" and "0".
2. The information input method described in Section 2, Section 2, or Section 3.