JPS6152027A - Multi-processing type counter - Google Patents

Abstract

PURPOSE:To attain measurement of long time with a counter of less number of bits and to improve the accuracy at measurement for a short time by switching an adding value fed to an adder depending on the count. CONSTITUTION:When a signal is inputted to an input terminal 1, an output data of a RAM3 is inputted to an adder 4. When a signal from a selector 9 goes to logical 1, the data is increased by 1 and then stored again to the RAM3. Two signals having a different period are fed to input terminals 6, 7 of the selector 9, which is switched by the output of a comparator 8 to which the output of the RAM3 is inputted. That is, when the output of the RAM3 is smaller than a prescribed value, a signal with a short period is outputted and when larger, a signal with a long period is outputted. Thus, long-time measurement is attained with a counter of less number of bits and the accuracy at short time measurement is kept high.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a multi-processing counter that is capable of measuring time with the required time accuracy from short to long periods of time even if the bit length of the adder is short. It is.

[Prior art]

Generally, when multiplexed signals are used, a multiprocessing counter is required to operate a counter for each signal. That is, FIG. 1 is a block diagram showing a conventional multi-processing counter. In the figure, 1 is an input terminal into which multiplexed signals are input, 2a to 2n are AND gates, 3 is a RAM, 4 is an adder, and 5 is, for example, a period T"'
This is a signal input terminal into which a 111 signal is input at 1m5ec.

Next, the operation of the multiprocessing counter with the above configuration will be explained. First, when a signal of '1/r level is input to input terminal 1, the output data of RAM3 is
It is input to the adder 4 via a to 2n.

Then, when the 11" signal is input to the signal input terminal 5, 1
is added, and the data of adder 4 is stored in RAM 3 again. Therefore, since the address of this RAM 3 changes depending on the multiplicity of signals, the data written in the command will be read out when the same address is reached next time. That is, since the data of one address is added every certain period, the plurality of colors as a whole operate as if they were performing separate counting operations according to the input signals. Next, when measuring time using this multi-processing type computer, the maximum amount of time that can be measured can be expressed by equation (1).

tmaX=T112n (seconds) (1) Here, T is the period n of the multi-processing type caranta and is the number of bits. For example, when 1m5ec+n=8 pits, tmax"256m5eC.

However, in the case of a conventional multiprocessing counter, when measurement over a long period of time is required, the amount of hardware increases if the period T of the multiprocessing counter is lengthened or the number of bits n is increased. Generally, when measuring a long time, accuracy is often not required as much as when measuring a short time. In such a case, if the multiprocessing counter is reset for a short time tl and a long time t! When trying to find out, the accuracy of time is determined by the short time t1, so the long time tsf! :In order to know, the number of bits n must be increased instead of increasing the period T, which increases the amount of hardware.

There were drawbacks such as leading to price increases.

[Summary of the invention]

Therefore, the object of the present invention is to use a limited number of bits to maintain measurement accuracy for a short period of time t1, while maintaining measurement accuracy for a long period of 1 g.
The present invention provides a multi-processing counter that enables measurement of .

In order to achieve such an object, the present invention utilizes a RAMtn
In a multi-processing counter equipped with a bit adder and n gate circuits, the adder added to the adder is selectively switched depending on the counter value to change it in stages. This will be explained in detail.

[Implementation sequence of the invention]

FIG. 2 is a block diagram showing an embodiment of a multi-processing type counter according to the present invention. In the same figure, 6 is a first signal input terminal to which a 11" signal is input with a period of T1 = 1 msec, for example, and 7 is a first signal input terminal with a period of T2 = m'p1" of 10 m3, for example.
eC is the second signal input terminal to which the 11' signal is input;
0110010), the comparator 9 outputs a switching signal when this switching signal is not input, the input signal 1 is output to the first input terminal 6, and when this switching signal is input, the comparator 9 outputs a switching signal. This is a selector from which the 11 signal input to the input terminal 7 is output.

Next, the operation of the multi-processing counter with the above configuration will be explained. First, the counter value of adder 4 is from 0 to 49.
Until then, the comparator 8 does not output a switching signal. Therefore, the period T1 of input to the first signal input terminal 6 is 1 ms.
The 11 signal of ec is input to the adder 4 via the selector 5, and is added by 1 at a period of Tl'' 1ms e C. When the counter value of the adder 4 reaches 50, the comparator 8 The counter value 50 of the adder 4 is detected and a switching signal is output. Therefore, the selector 9 is switched by inputting this switching signal. 1. The signal is input to the adder 4 via the selector 9. Therefore, the adder 4 adds 1 at a time period of Ts 10m5ec, and in the case of 8 bits, the signal is added by 1 at a cycle of Ts 10m5ec. It is possible to count up to In this way, the counter value of the adder 4 is from O to 50,
That is, up to 50 maeC can be measured with 1m5ecOf7 degrees, and when the counter value is from 51 to 255, that is, from 51m5ec to 2100m5ec (2.1 seconds), it can be measured with an accuracy of 10m5eC.

In addition, although the above explanation shows the case where one comparator is provided, it is not limited to this, and by providing multiple comparators and changing the S accuracy in stages, it is possible to measure for a longer time. Of course it will happen.

In other words, although the case where the adder 4 is configured with 8 bits has been described, the present invention is not limited to this, and it goes without saying that the adder 4 can be configured with any number of pits.

〔Effect of the invention〕

As explained in detail above, the multi-processing counter according to the present invention has advantages such as being able to perform long-term measurements with a counter with a small pit length and maintaining sufficiently high accuracy during short-time measurements. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional multiprocessing counter.
FIG. 2 is a block diagram showing an embodiment of a multi-processing type counter according to the present invention. 1...Input terminal, 2a-2n...AND gate, 3...Fist/RAM, 4...φ/Φ adder, 5-
・Conflict signal input terminal, 6...1st signal input terminal, 7.
...Second signal input terminal, 8 ms-comparator, 9...
・Selector.

Claims (1)

[Claims] In a multi-processing counter equipped with a RAM, an n-pit adder, and n gate circuits, the added value added to the adder is selectively switched depending on the value of the counter, and is changed in stages. Multi-processing counter.