JPS6150357B2 - - Google Patents
Info
- Publication number
- JPS6150357B2 JPS6150357B2 JP17717981A JP17717981A JPS6150357B2 JP S6150357 B2 JPS6150357 B2 JP S6150357B2 JP 17717981 A JP17717981 A JP 17717981A JP 17717981 A JP17717981 A JP 17717981A JP S6150357 B2 JPS6150357 B2 JP S6150357B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- memory
- bank
- service
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17717981A JPS5880756A (ja) | 1981-11-06 | 1981-11-06 | デ−タ処理装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17717981A JPS5880756A (ja) | 1981-11-06 | 1981-11-06 | デ−タ処理装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5880756A JPS5880756A (ja) | 1983-05-14 |
| JPS6150357B2 true JPS6150357B2 (enrdf_load_stackoverflow) | 1986-11-04 |
Family
ID=16026556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17717981A Granted JPS5880756A (ja) | 1981-11-06 | 1981-11-06 | デ−タ処理装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5880756A (enrdf_load_stackoverflow) |
-
1981
- 1981-11-06 JP JP17717981A patent/JPS5880756A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5880756A (ja) | 1983-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0476990A2 (en) | Dynamic bus arbitration | |
| US4785394A (en) | Fair arbitration technique for a split transaction bus in a multiprocessor computer system | |
| US5790813A (en) | Pre-arbitration system allowing look-around and bypass for significant operations | |
| EP0428330A2 (en) | Computer interface circuit | |
| US5274785A (en) | Round robin arbiter circuit apparatus | |
| US5241629A (en) | Method and apparatus for a high performance round robin distributed bus priority network | |
| JPS6150357B2 (enrdf_load_stackoverflow) | ||
| US5446847A (en) | Programmable system bus priority network | |
| JPH06161873A (ja) | 主記憶に対する複数のアクセスポイントのハングアップ処理方式 | |
| JPH0562384B2 (enrdf_load_stackoverflow) | ||
| JPS61248153A (ja) | マルチプロセツサシステムにおけるメモリアクセス制御方式 | |
| JPS6240565A (ja) | メモリ制御方式 | |
| JP2903551B2 (ja) | マルチプロセッサの同期化機構 | |
| JPH039497B2 (enrdf_load_stackoverflow) | ||
| JPS6126104B2 (enrdf_load_stackoverflow) | ||
| JPH04296963A (ja) | マルチプロセッサシステム | |
| JPS5840215B2 (ja) | システム同期方式 | |
| JPH04308955A (ja) | マルチプロセッサ装置 | |
| KR100243868B1 (ko) | 주 전산기에서의 중재로직 방법 | |
| JP2713204B2 (ja) | 情報処理システム | |
| JPH08180027A (ja) | 調停回路 | |
| JP2836591B2 (ja) | プロセッサ間バス伝送方法及びプロセッサ間バス伝送システム | |
| JP2856709B2 (ja) | バス間結合システム | |
| JPS6363939B2 (enrdf_load_stackoverflow) | ||
| JPS6059464A (ja) | バスリクエスト制御方式 |