JPS6146055A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6146055A JPS6146055A JP16746484A JP16746484A JPS6146055A JP S6146055 A JPS6146055 A JP S6146055A JP 16746484 A JP16746484 A JP 16746484A JP 16746484 A JP16746484 A JP 16746484A JP S6146055 A JPS6146055 A JP S6146055A
- Authority
- JP
- Japan
- Prior art keywords
- tin
- layer
- lead
- copper
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
イ、産業上の利用分野
本発明は、半導体装置に係り、特に、電気接続のため外
装体の外部に引出した外部リードの構造に関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor device, and more particularly to the structure of an external lead drawn out of an exterior body for electrical connection.
口、従来の技術
一般に、ICやトジンジスタなどの半導体装置における
外部リードは、素材のコバールや銅系材料に金メッキや
錫メツキを施こした構造をしている◎その理由は、半導
体装置の外部リード機能として、外部環境から外部リー
ドの腐食を防止し、外部リードと外部回路との電気的接
続を容易ならしめ、また、外部リードと外部回路との半
田付は接続の半田付は性を確保するためである。しかし
、金メッキは高価で多るため、セラミックパッケージな
どの特殊外装の製品に適用されているが、一般には、錫
メッキが広く使用されている。錫メッキを用いる場合、
一般的に、第2図の断面図に示す構造をしている。第2
図においてコバールや銅系材料からできている素材1の
上に、銅メッキ2を施し、その上に、錫メッキ3を施し
ている。銅メッキ2は、素材がコバールの場合、錫の密
着性を上げるため、また素材が銅系材料の場合、銅系材
料中の亜鉛等が錫メツキ中に拡散し、変色や半田付は性
の低下をまねくのを防止するため設けている。Conventional technology Generally speaking, the external leads of semiconductor devices such as ICs and digital resistors have a structure in which the material Kovar or copper-based material is plated with gold or tin.The reason for this is that the external leads of semiconductor devices As a function, it prevents corrosion of the external leads from the external environment, facilitates the electrical connection between the external leads and the external circuit, and also ensures the soldering properties of the connections between the external leads and the external circuit. It's for a reason. However, since gold plating is expensive and plentiful, it is applied to products with special exteriors such as ceramic packages, but in general, tin plating is widely used. When using tin plating,
Generally, the structure is shown in the cross-sectional view of FIG. Second
In the figure, a copper plating 2 is applied on a material 1 made of Kovar or a copper-based material, and a tin plating 3 is applied thereon. Copper plating 2 is used to increase the adhesion of tin when the material is Kovar, and when the material is a copper-based material, zinc etc. in the copper-based material will diffuse into the tin plating, causing discoloration and soldering. This is provided to prevent this from occurring.
しかしながら、前記構造では、長期保管の間に、銅と錫
の間で合金が成長し、銅−錫合金が硬くもろいため、銅
と銅−錫合金の間で剥離を引き起すことがある。また、
銅−錫合金は半田付は性が悪く半導体装置の外部リード
機能を損ねている。さらに悪いことに、合金の成長によ
シ錫メッチ中にひずみが生じ、ホイスカー発生の原因に
もなる。However, in this structure, during long-term storage, an alloy grows between the copper and tin, which may cause delamination between the copper and the copper-tin alloy, since the copper-tin alloy is hard and brittle. Also,
Copper-tin alloy has poor soldering properties and impairs the external lead function of semiconductor devices. To make matters worse, the growth of the alloy causes distortion during the tin etch, causing whiskers.
ハ0発明が解決しようとする問題点
上述のような、銅層の上に錫メッキした表層構造の従来
の外部リードでは、長期間保管中に前記鋼と錫の間で合
金を作シ、外部リードとして・の機能を損うようになる
点が問題であった。Problems to be Solved by the Invention In the conventional external lead having a surface layer structure in which tin is plated on a copper layer as described above, an alloy is formed between the steel and tin during long-term storage. The problem was that it began to impair its function as a lead.
二0問題点を解決するための技術手段
上記問題に対し、本発明の半導体装置における外部リー
ドでは、コバール、銅系材料などの素材金属の上に銅層
を設け、その上に銀層を設け、さらにその上に錫−鉛の
合金層を設けた断面構造としている。20 Technical Means for Solving the Problems To solve the above problems, in the external leads of the semiconductor device of the present invention, a copper layer is provided on a material metal such as Kovar or a copper-based material, and a silver layer is provided on top of the copper layer. , and further has a cross-sectional structure with a tin-lead alloy layer provided thereon.
ホ0作用
本発明の外部リードにおける銅層は、銀メッキの密着性
をよくシ、不純物拡散の防止をする。−釜外側の錫−鉛
合金にホイスヤの発生が少く半田付は性をよくしている
。Function The copper layer in the external lead of the present invention improves the adhesion of silver plating and prevents impurity diffusion. - The tin-lead alloy on the outside of the hook has less cracking and has good soldering properties.
へ、実施例
つぎに本発明を実施例によシ説明する0第1図は本発明
の一実施例の断面図である。第1図において、1は、亜
鉛を含む銅系の合金、筐たは、コバールからなる素材で
アシ、その上に銅層2が設けられている0さらに、銅R
II2の上に、銀メッキNi4.さらに銀メッキ層の上
に、錫−鉛合金のメッキ5が施されている。この錫−鉛
合金5の鉛含v蛍は、銀と錫の合金成長のため錫が減少
するので、鉛の含有量を比較的少くする0鉛の含有量が
多くなシ過ぎると、融点が上9半田付性が悪くなること
からも、鉛含有量は2〜50wt%が妥当なところであ
る。EXAMPLE Next, the present invention will be explained by way of an example. FIG. 1 is a sectional view of an example of the present invention. In FIG. 1, 1 is a copper-based alloy containing zinc, a casing or a material made of Kovar, and a copper layer 2 is provided thereon.
On top of II2, silver plating Ni4. Furthermore, a tin-lead alloy plating 5 is applied on the silver plating layer. The lead content of this tin-lead alloy 5 decreases due to the alloy growth of silver and tin, so if the lead content is too high, the melting point will decrease. Top 9: Since solderability deteriorates, a lead content of 2 to 50 wt% is appropriate.
ト1発明の効果
本発明に係る外部リードでは、従来直接績していた銅層
と錫メッキとの間に銀の層を介在させて、有害な銅と錫
の合金化を防止すると共に、錫の代わシに錫−鉛合金に
美えてホイスカの発生を防止して半田付は性の改善を図
シ、長期間の保管にお−て、外部リード機能の劣化が発
生しない01. Effects of the Invention In the external lead according to the present invention, a silver layer is interposed between the copper layer and the tin plating, which were conventionally directly bonded, to prevent harmful alloying of copper and tin, and to prevent tin plating. Instead, the tin-lead alloy prevents the generation of whiskers and improves solderability, and the external lead function does not deteriorate during long-term storage.
第1図は本発明の一実施例に係る外部リードの断面図、
第2図は従来の外部リードの断面図である0
1・・・・・・素材叛属、2・・・・・・銅層、3・・
・・・・錫メッキ層、4・・・・・・銀層、5・・・・
・・錫−釦付金層。FIG. 1 is a sectional view of an external lead according to an embodiment of the present invention;
Fig. 2 is a cross-sectional view of a conventional external lead.
...Tin plating layer, 4...Silver layer, 5...
・・Tin-gold layer with button.
Claims (1)
において、前記外部リードは、素材金属の上に銅層を設
け、その上に銀層を設け、さらにその上に錫−鉛の合金
層を設けてなることを特徴とする半導体装置。In a semiconductor device having an external lead that is pulled out from the exterior body, the external lead is provided with a copper layer on a material metal, a silver layer on top of the copper layer, and a tin-lead alloy layer on top of the copper layer. A semiconductor device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16746484A JPS6146055A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16746484A JPS6146055A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6146055A true JPS6146055A (en) | 1986-03-06 |
Family
ID=15850160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16746484A Pending JPS6146055A (en) | 1984-08-10 | 1984-08-10 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6146055A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014042002A (en) * | 2003-10-14 | 2014-03-06 | Olin Corp | Fretting and whisker resistant coating system and method |
-
1984
- 1984-08-10 JP JP16746484A patent/JPS6146055A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014042002A (en) * | 2003-10-14 | 2014-03-06 | Olin Corp | Fretting and whisker resistant coating system and method |
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