JPS6145319B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory that can improve reliability.

In general, non-volatile semiconductor memories that use MOS field effect transistors (MOS FETs) with a floating gate configuration as memory cells can have their memory contents rewritten many times, so they have become more popular with the spread of microcomputers, etc. It has become widely used. MOS with this floating gate structure
As is well known, an FET consists of a diffusion region formed in a semiconductor substrate, a floating gate, and a control gate. And when electrons are injected into the floating gate,
It does not conduct even if a predetermined potential (for example, 5V) is applied to the control gate, and conducts when the floating gate is in a neutral state. Therefore, information of "0" and "1" can be stored depending on the conduction state of the transistor.

By the way, when injecting electrons into the floating gate, a high voltage (20V~20V) is applied to the control gate and drain.
25V) is applied, and among the electron-hole pairs generated by impact ionization that occurs in the pinch-off region of the channel region near the drain, electrons are injected into the floating gate. Such a pinch-off region is
It is well known that this occurs when a MOS transistor performs pentode operation. If this memory cell is used in a state where the transistor operates as a pentode, it will be in the read state, that is, the drain,
Even when no high voltage is applied between the control gates, the pinch-off region exists, resulting in impact ionization. In this case, since the voltage is low (5V), the channel current is small, and only a few electron-hole pairs are generated, and although the probability is extremely small, electrons are injected into the floating gate little by little.
Therefore, after long-term use, there is a risk that electrons will accumulate in the floating gate and the stored contents will change. For this reason, the drain voltage of the memory cell is set lower than the gate voltage, and the transistor is used in a state where it performs triode operation without creating the pinch-off region.

FIG. 1 is a circuit diagram of such a nonvolatile semiconductor memory. That is, it corresponds to each section set by a plurality of row lines R ₁ to _{R n} set in one specified direction and a plurality of column lines S ₁ to _{S o} set perpendicular to the row lines. Then, memory cell M ₁₁ ~
M _no is placed. Then, the row line performs switching control on the memory cells using the control signal from the row decoder, and the column line uses the output from the column decoder to perform switching control on the column gate transistors T ₁ to _{T o} to read information in the memory cells. Or writing to memory cells. Furthermore, a power supply circuit composed of transistors T _r1 to _{T r4} is provided to supply power to the drains of the memory cells. This circuit is for setting the drain voltage of the memory cell low, and the transistors T _r3 and T
A predetermined potential is set by _r4 , and transistors T _r1 and T _r
The gate voltage of ₂ is set low to make it conductive, and power is supplied to the drain of the memory cell. Furthermore, a depletion transistor T _r5 serving as a load element is disposed between the transistor T _r2 and a transistor T _r11 constituting a differential sense amplifier 11, which will be described later _. The amplitude of the column line potential (signals read from memory cells M ₁₁ to M _no ) supplied to the gates is increased. The above differential sense amplifier 11
is composed of transistors T _{r6 and} T _r14 , and detects the potential difference between the gate side input potentials V _A and V _B of the transistors T _r11 and T _r13 , and based on this detected value,
The signal A is supplied to the output buffer circuit at the next stage. A comparison potential generation circuit 12 is provided at the other input end of the differential sense amplifier 11.
This comparison potential generation circuit 12 includes a transistor T _r
1 ' to T _r5 ', a transistor T ₁ ', and a transistor M' which has the same structure as the memory cell. input potential V _B
This is to prevent changes in the reading speed of "0" and "1" due to changes in the threshold voltage of the memory cell. Control potential generation circuit 1 for controlling conduction of transistor M' of the comparison potential generation circuit 12
3 are depletion type transistors T _r15 and T _r1 which are connected in series between the power supply Vc and the ground point V _s , and whose gates are connected to the power supply Vc and the ground point V _s .
₆ .

Incidentally, the column line potential V _A supplied from the memory cell has two types of voltage values depending on the storage contents of the transistors M ₁₁ to _{M no} , that is, the memory cell. When the stored content is "0", the memory cell is not turned on even if a voltage is applied to the gate of the memory cell, and when the stored content is "1", the selected memory cell is turned on. The column line potential of this selected memory cell gradually begins to fall, and the second
It will look like the section shown by A in the figure. "0" depending on whether the column line potential at this time is higher or lower than the comparison potential.
Alternatively, a state of "1" is set. Therefore, as shown by the solid line 14 and the broken line 15 in FIG. 2, if the threshold voltage V _th of the memory cell changes, the output characteristics change. That is, for example, when the threshold voltage V _th of a memory cell increases,
As the memory cell current decreases, the column line discharge time slows down (solid line 14 in FIG. 2). In contrast,
The column lines charge faster, creating an imbalance in the read speeds of "1" and "0". For this reason,
Using a transistor M′ equivalent to a memory cell,
Correction is made by changing the comparison potential in response to changes in the threshold voltage V _th of the memory cell (second
solid line 14' and dashed line 15'). Corresponding to the solid line 14 in FIG. 2, 14' is the comparison potential.
The comparison potential corresponding to the broken line 15 in FIG. 2 in which the charging/discharging time of the column line has changed due to the change in the threshold voltage of the memory cell is the broken line 15' in FIG. Even if the threshold voltage of the memory cell changes, the column line potential and the comparison potential intersect at the same place (at the same time) during both charging and discharging, as shown by the dashed line in FIG.
In other words, the threshold voltage of the memory cell changes,
As a result, even if the column line charging/discharging time changes,
There is no change in the reading speed of "0" and "1" since the comparison potential changes accordingly.

FIGS. 3a and 3b show other examples of circuits that generate the control potential V _R for controlling the transistor M'. In figure a, transistors T _r17 and T _r18 are connected in series and provided between the power supply Vc and the ground point V _s . The gate of the transistor T _r17 is connected to the power supply V _c , the gate of the transistor T _r18 is connected to the connection point between the transistors T _r17 and T _r18 , and the output V _R is obtained from this connection point.

Furthermore, in figure b, a depletion type transistor T _r1 is connected between the power supply V _c and the ground point.
₉ , T _r20 are connected in series. Then, the gate of transistor T _r19 is connected to transistors T _r19 and T _r2
0 connection point, and the gate of the transistor T _r20 is connected to the ground point V _s , and an output V _R is obtained from this connection point. Both figures a and b show the same circuit operation as the circuit shown in FIG.

By the way, in the circuits shown in FIG. 1 and FIGS. 3a and 3b, the gate potential of the transistor M' equivalent to the memory cell, that is, the output V _R of the control potential generation circuit 13 has a value lower than the power supply V _c . ing. Further, the gate potential of a regular memory cell, that is, the row line potential, is at the same level as the power supply V _c when selected. Therefore, the transistor M' equivalent to this memory cell operates more like a pentode than a regular memory cell. Furthermore, due to variations in threshold voltage caused by the manufacturing process, variations in transistor dimensions, etc., there is a risk that transistor M' may operate as a pentode. Furthermore, a regular memory cell has a selected and non-selected state, and a voltage is not always applied to the drain and gate, but a voltage is always applied to the transistor M'. Therefore, it is subjected to greater stress than regular memory cells. For these reasons, using a transistor equivalent to a memory cell to generate a comparison potential poses a problem in terms of reliability.

The present invention was made in view of the above circumstances, and its purpose is to provide a highly reliable nonvolatile semiconductor memory.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 4 shows a control potential generation circuit according to the present invention. In this circuit, the output potential V _B is changed in response to changes in the threshold voltage of the memory cell without using a transistor equivalent to the memory cell in the comparison potential generation circuit.

That is, a depletion type transistor T _r2 is connected in series between the power supply V _c and the ground point V _s .
₁ , T _r22 are provided, and these transistors T _r21 , T _r22
A predetermined potential is supplied from the connection point to the gate of the transistor T _r23 . A transistor T _r24 is connected in series with this transistor T _r23 and inserted between the power supply V _c and the ground point V _s . Then, an output V _R is obtained from the connection point between the transistors T _r23 and T _r24 .

The transistor T _r23 has a single gate structure by connecting a floating gate electrode of a transistor equivalent to a memory cell and a control gate electrode, and this floating gate is used as a control gate. In other words, it has a normal floating gate structure.
The MOS transistor, as shown in Figure 5a,
An N ⁺ type diffusion region 1 is formed on a P type semiconductor substrate 16.
7 and 18 are provided as a source and a drain.
Then, on this substrate 16, an electrically insulated floating gate 19 is provided, and furthermore, this floating gate 1
It has a two-layer gate structure in which a control gate electrode 20 for controlling the current flowing through the memory cell is provided on top of the memory cell.

On the other hand, the transistor T _r23 is
As shown in FIG. 2, a control gate electrode 21 is connected to a floating gate 19. This transistor T _r23 is removed at the same manufacturing stage as the memory cell, for example with a contact mask, so that the floating gate 19
Then, a contact hole is made in the control gate 21,
Formed by connecting with aluminum etc.
Therefore, there is a one-to-one correspondence between the threshold voltage of the memory cell and the threshold voltage of the transistor T _r23 .

By the way, the common connection point of the transistors T _r21 and T _r22 has a potential lower by a certain potential than the power supply V _c .
If the potential at this point is _VX , then _VR = Vx - _{V th23} - α V _th23 : Threshold voltage of transistor T _r23 α : Voltage drop due to transistor T _r24 . Therefore, the output V _R of this circuit depends on the threshold voltage of the transistor T _r23 ; as the threshold voltage V _th23 increases, the output V _R decreases, and as the threshold voltage V _th23 decreases, the output decreases. V _R becomes high.

The above-mentioned control potential generation circuit is implemented as a control potential generation circuit 1 for a nonvolatile semiconductor memory shown in FIG.
Use in place of 3. A transistor equivalent to the memory cell of the comparison potential generation circuit 12
A normal enhancement type MOS transistor is provided as a dummy cell instead of M' (dummy cell).

Here, if the threshold voltage V _th of the memory cell increases for some reason, the memory cell current decreases, the column line discharge speed decreases, and the "0" stable point of the column line potential also increases. However, since the control potential generation circuit shown in FIG. 4 is used, in response to the increase in the threshold voltage V _th of the memory cell,
Since the threshold voltage V _th23 of the transistor T _r23 increases, the output potential V _R decreases. Therefore,
There is no need to use a transistor M' equivalent to a memory cell, and even if a normal enhancement type transistor is used, the conduction resistance increases, and the output potential V _B of the comparison potential generation circuit 12 increases.

That is, the comparison potential of the differential sense amplifier 11 rises, and this sense amplifier senses at a higher potential than usual. Therefore, even if the conduction resistance of the memory cell increases and the discharge speed of the column line slows down, the detection speed remains unchanged because the detection level of the potential of the sensor amplifier increases. Further, since a normal enhancement type transistor can be used as the transistor M' equivalent to the memory cell of the comparison potential generation circuit 12, reliability can be improved. Instead of the transistor M' which is equivalent to the memory cell of the comparison potential generation circuit 12, a transistor having a floating gate and a control gate connected may be used like the transistor T _r23 .

When this is done, the change in threshold voltage is further magnified.

6 and 7 respectively show other embodiments of the present invention, and show other examples of control potential generation circuits. That is, in FIG. 6, a transistor T _r25 whose floating gate and control gate are short-circuited and a depletion type transistor T _r26 are connected in series between the power supply V _c and the ground point V _s .

Then, the gate of the transistor T _r25 is connected to the power supply V _c
, the gate of transistor T _r26 is connected to the ground point V _s ,
These transistors T _r25 and T _r26 are connected respectively.
The output V _R is obtained from the common connection point of the two.

According to such a configuration, the output V _R is as follows: V _R =V _c −V _th25 −β V _th25 :
Threshold voltage V _th β of transistor T _r25 : Voltage drop due to transistor T _r26 . Therefore, in this circuit as well, the output V _R depends on the threshold voltage V _th25 of the transistor T _r25 .

Furthermore, FIG. 7 shows a combination of the circuits shown in FIGS. 4 and 6. According to such a configuration, _the output _V and output.

Furthermore, in the embodiment, a normal enhancement type transistor was used instead of the transistor M' of the comparison potential generation circuit 12, but a transistor M' equivalent to a memory cell with its floating gate and control gate connected was used. Figures 4 and 6
By providing the control potential generation circuit shown in FIGS. 7 and 7, changes in the threshold voltage V _th of the memory cell can be expanded and output.

As explained above, according to the present invention, the read speed does not change due to changes in the threshold voltage of the memory cell, and the transistor M′ equivalent to the memory cell is not used in the comparison potential generation circuit. Since the input V _B of the differential sense amplifier can be changed, a highly reliable nonvolatile semiconductor memory can be obtained.

Note that the present invention is not limited to the above-described embodiments, but may be configured to change the comparison potential supplied to the differential sense amplifier in response to changes in the threshold voltage of the memory cell. good. Therefore, for example, by replacing the transistors T _r3 ′ and T _r4 ′ in the comparison potential generation circuit 12 of FIG. 1 with the control potential generation circuits shown in FIGS. 4, 6, and 7, A potential V _B may also be obtained.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional nonvolatile semiconductor memory, Figure 2 is a characteristic diagram of a memory cell with a floating gate structure, and Figures 3a and 3b are control potential generation circuits in the circuit shown in Figure 1 above. 4 is a circuit diagram showing a control potential generation circuit according to an embodiment of the present invention, and FIGS. 5a and 5b are a cross-sectional configuration diagram of a floating gate type MOS FET, and The cross-sectional configuration diagram of the floating gate type MOSFET used in the invention, FIG. 6, and FIG. 7 are diagrams showing control potential generation circuits showing other embodiments of the invention, respectively. R ₁ ~ _{R n} ... Row line, S ₁ ~ _{S o} ... Column line, M ₁₁ ~ M
_no ...memory cell, 11...differential sense amplifier, 12...comparison potential generation circuit, 13...control potential generation circuit.

Claims (1)

[Claims] 1 Floating gate gate structure arranged corresponding to each section defined by multiple row lines and multiple column lines
A memory cell consisting of a MOS transistor, a differential sense amplifier to which one input signal is supplied from the above column line, and a potential corresponding to the threshold voltage of the memory cell as the other input signal of this differential sense amplifier. a comparison potential generation circuit equipped with an enhancement type MOS transistor of a single gate structure as a dummy cell for the memory cell that supplies the above memory cell; A non-volatile device comprising a control potential generation circuit having a MOS transistor and coupled to the comparison potential generation circuit to set the output of the comparison potential generation circuit to a potential corresponding to the threshold voltage of the memory cell. sexual semiconductor memory.