JPS6412039B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory that can improve reliability.

In general, non-volatile semiconductor memories whose memory cells are MOS field effect transistors (MOS FETs) with a floating gate configuration can have their memory contents rewritten many times, so they have become more popular with the spread of microcomputers, etc. It has become widely used. MOS with this floating gate structure
As is well known, an FET consists of a diffusion region formed in a semiconductor substrate, a floating gate, and a control gate. When electrons are injected into the floating gate, the control gate does not conduct even if a predetermined potential (for example, 5V) is applied to it, but when the floating gate is in a neutral state, it conducts. Therefore, information of "0" and "1" can be stored depending on the conduction state of the transistor.

By the way, when injecting electrons into the floating gate, a high voltage (20V~20V) is applied to the control gate and drain.
25V) is applied, and among the electron-hole pairs generated by impact ionization that occurs in the pinch-off region of the channel region near the drain, electrons are injected into the floating gate. Such a pinch-off region is
It is well known that this occurs when a MOS transistor performs pentode operation. If this memory cell is used in a state where the transistor operates as a pentode, it will be in the read state, that is, the drain,
Even when no high voltage is applied between the control gates, the pinch-off region exists, resulting in impact ionization. In this case, since the voltage is low (5V), the channel current is small, and only a few electron-hole pairs are generated, and although the probability is extremely small, electrons are injected into the floating gate little by little.
Therefore, after long-term use, there is a risk that electrons will accumulate in the floating gate and the stored contents will change. For this reason, the drain voltage of the memory cell is set lower than the gate voltage, and the transistor is used in a state where it performs triode operation without creating the pinch-off region.

FIG. 1 is a circuit diagram of such a nonvolatile semiconductor memory. That is, each intersection position is set by a plurality of row lines R ₁ to _{R n} that are set in one specified direction, and a plurality of column lines S ₁ to _{S o} that are set to directly illuminate the row lines. Corresponding to memory cell M ₁₁
~M _no is placed. Then, the row line controls switching of the memory cells by the control signal of the row decoder, and the column line controls the switching of the column gate transistors T ₁ to _{T o} by the output of the column decoder.
Information in the memory cell is read or written to the memory cell. Furthermore, a power supply circuit composed of transistors Tr ₁ to _{Tr 4} is provided to supply power to the drains of the memory cells. This circuit is to set the drain voltage of the memory cell low, and the transistors Tr ₃ ,
A predetermined potential is set by Tr ₄ , and transistors Tr ₁ ,
The gate voltage of Tr ₂ is set low to make it conductive and supply power to the drain of the memory cell. Also,
Between the transistor Tr ₂ and the transistor Tr ₁₁ that constitutes a differential sense amplifier 11 to be described later,
The amplitude of the column line potential (signal read from memory cells _M11 to _Mno ) supplied to the gate of transistor _Tr11 is determined by arranging a depletion type transistor _Tr5 that acts as a load element and supplying power supply _Vc . is increasing. The above differential sense amplifier 11
is composed of transistors Tr ₆ to Tr ₁₄ ,
The potential difference between the gate side input potentials V _A and V _B of transistors Tr ₁₁ and Tr ₁₃ is detected, and based on this detected value,
The signal A is supplied to the output buffer circuit at the next stage. A comparison potential generation circuit 12 is provided at the other input end of the differential sense amplifier 11 .
This comparison potential generation circuit 12 includes a transistor
It is composed of transistors Tr ₁ ′ to Tr ₅ ′, transistor T ₁ ′, and transistor M′, which has the same structure as the memory cell. Sense amplifier input potential
This is to control _VB and prevent changes in the reading speed of "0" and "1" due to changes in the threshold voltage of the memory cell. The control potential generation circuit 13 that controls conduction of the transistor M' of the comparison potential generation circuit 12 is connected in series between the power supply V _C and the ground point V _S , and has a gate connected to the power supply V _C and the ground point V _S. In addition, depletion type transistor Tr ₁₅ ,
Composed by Tr ₁₆ .

By the way, the column line potential supplied from the memory cell
V _A has two types of voltage values depending on the storage contents of the transistors M ₁₁ to _{M no} , that is, the memory cells. When the stored content is "0", the memory cell is not turned on even if a voltage is applied to the gate of the memory cell, and when the stored content is "1", the selected memory cell is turned on. The column line potential of the selected memory cell gradually begins to fall, becoming like the section indicated by A in FIG. "0" depending on whether the column line potential at this time is higher or lower than the comparison potential.
Alternatively, a state of "1" is set. Therefore, as shown by the solid line 14 and broken line 15 in FIG. 2, if the threshold voltage V _th of the memory cell changes, the output characteristics change. That is, for example, when the threshold voltage V _th of a memory cell increases,
As the memory cell current decreases, the column line discharge time slows down (solid line 14 in FIG. 2). On the other hand,
The column lines charge faster, creating an imbalance in the read speeds of "1" and "0". For this reason,
Using a transistor M′ equivalent to a memory cell,
Correction is made by changing the comparison potential in response to changes in the threshold voltage V _th of the memory cell (second
solid line 14' and dashed line 15'). Corresponding to the solid line 14 in FIG. 2, 14' is the comparison potential.
The comparison potential corresponding to the broken line 15 in FIG. 2 in which the charging/discharging time of the column line has changed due to the change in the threshold voltage of the memory cell is the broken line 15' in FIG. Even if the threshold voltage of the memory cell changes, the column line potential and the comparison potential intersect at the same place (at the same time) in both charging and discharging, as shown by the dashed line in FIG.
In other words, the threshold voltage of the memory cell changes,
As a result, even if the column line charging/discharging time changes,
There is no change in the reading speed of "0" and "1" since the comparison potential changes accordingly.

By the way, in the circuit shown in FIG. 1, the gate potential of the transistor M' equivalent to the memory cell, that is, the output V _R of the control potential generation circuit 13 , is equal to the power supply V _C
It has become a lower value. Further, the gate potential of a regular memory cell, that is, the row line potential, becomes the same level as the power supply V _C when selected. Therefore,
A transistor M' equivalent to this memory cell operates more like a pentode than a regular memory cell. Furthermore, due to variations in threshold voltage caused by the manufacturing process, variations in transistor dimensions, etc., there is a risk that transistor M' may operate as a pentode. Furthermore, a regular memory cell has a state of selection, non-selection, or power down, and a voltage is not always applied to the drain and gate, but a voltage is always applied to the transistor M'. Therefore, it is subjected to greater stress than regular memory cells. For these reasons, it is not preferable from the viewpoint of reliability to use a transistor equivalent to a memory cell for generating a comparison potential.

This invention was made in view of the above-mentioned circumstances, and its purpose is to reduce stress on transistors equivalent to memory cells provided for generating comparison potentials, thereby increasing reliability. An object of the present invention is to provide a non-volatile semiconductor memory.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows its configuration. Some recent memories are put into a power-down mode in order to reduce current consumption when they are in a non-operating state, but in this invention, in this power-down mode, a transistor M' equivalent to a memory cell is used. This prevents voltage from being applied to both. That is, a transistor is connected to the power supply V _C side of the comparison potential generation circuit 12 and control potential generation circuit 13 described above.
Tr ₁₇ to Tr ₂₀ are added, and a power down signal is supplied to the gates of these transistors. Also, the gate of transistor T ₁ ′ is also connected to the power supply.
The above power down signal is applied instead of V _C. This power down signal is set to "0" to turn off the transistors Tr ₁₇ to Tr ₂₀ during power down, and is set to "1" to turn on the transistors during normal operation.

According to such a configuration, not only can the current supply to the transistor M' be prevented from being stressed during power down, but also the current consumption of the comparison potential generation circuit 12 and the control potential generation circuit 13 can be reduced to almost zero. can.

Note that in the circuit shown in Figure 3, the transistor
It is not necessary to provide all of Tr ₁₇ to Tr ₂₀ ; for example, it is sufficient to simply supply a power down signal to the gate of transistor T ₁ '. Also, transistor Tr ₁₈
The stress on transistor M' can also be reduced even if only one is provided to block current supply during power down.
Alternatively, any one of transistors Tr ₁₇ to Tr ₂₀ may be provided.

FIG. 4 shows another embodiment of the present invention, in which transistors T ₁ ' and M' constituting the comparison potential generation circuit 12 are provided in the same number as the column gate transistors, and are arranged to correspond to the selected column of memory cells. In this case, only the transistor M' that operates is operated. Here, the transistors T _1-1 ′ to _{T 1-o} ′ are transistors equivalent to column gate transistors, and the outputs C ₁ to _Co of the column decoder are supplied to their gates.

According to such a configuration, a voltage is applied to the drain of the transistor M' when that column is selected, that is, when the transistors _T1-1 ' to
Since this occurs only when one of T _1-o ′ is selected and turned on, the stress applied to the transistor M′ can be significantly reduced. Of course, this circuit can be used in combination with the circuit shown in Figure 3, and
Although this circuit uses the output signals C ₁ -C _o of the column decoder, these signals may also be column address outputs, and in this case, the number of transistors M' can be reduced. However, reducing the number of transistors M' increases the stress applied to each transistor.

Figures 5a and 5b are circuit diagrams showing still other embodiments, in which the conduction of transistors equivalent to memory cells is controlled using signals VR ₁ to _{VR n} generated from the output signals of the row decoder. It is something to do. That is, the circuit _shown in FIG . Then, the output signal of the row decoder is supplied to the gate of the transistor _Tr20 . When the output signal of the row decoder is "0", the output VR of the control potential generation circuit 13 shown in FIG. Set. Note that although the power down signal is supplied to the gate of the transistor T ₁ ', the power supply V _C may also be supplied.

According to such a configuration, the gate of the transistor M' corresponding to the selected row line becomes "1",
Since no potential is supplied to the gates of the other transistors M', stress on the transistors M' can be reduced.

Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented by combining the above-mentioned circuits. For example, the circuit shown in Figure 3 and the circuit shown in Figure 5
A combination of the circuits shown in the figure, or the circuit shown in Fig. 4 and the circuit shown in Fig. 5, and the circuit shown in Fig.
If the circuits shown in Fig. 4 and Fig. 5 are used together,
The stress applied to transistor M' can be further reduced.

As described above, according to the present invention, it is possible to reduce the stress on the transistor equivalent to the memory cell used in the comparison potential generation circuit, so that a more reliable nonvolatile semiconductor memory can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional non-volatile semiconductor memory, FIG. 2 is a characteristic diagram for data reading of a memory cell having a floating gate structure, and FIG. 3 is a diagram of a non-volatile semiconductor memory according to an embodiment of the present invention. 4 and 5a and 5b are diagrams showing other embodiments of the present invention, respectively, showing a comparison potential generation circuit and a control potential generation circuit. R ₁ ~ R _n row lines, S ₁ ~ _{S o} ... column lines, M ₁₁ ~ M _no ...
...Memory cell, 11 ...Differential sense amplifier, 1
2... Comparison potential generation circuit, 13 ... Control potential generation circuit, Tr ₁₇ to Tr ₂₀ ... Transistor,... Power down signal.

Claims (1)

[Claims] 1. A memory cell arranged corresponding to each intersection position set by a plurality of row lines and a plurality of column lines, and a differential type in which one input signal is supplied from the column line. A sense amplifier, a comparison potential generation circuit that supplies a potential corresponding to the threshold voltage of a memory cell as the other input signal of this differential sense amplifier, and a transistor equivalent to the memory cell that constitutes this comparison potential generation circuit. and a control potential generation circuit that controls conduction of a transistor equivalent to a memory cell of the comparison potential generation circuit. 2. As a means for controlling the conduction of a transistor equivalent to the above memory cell, a transistor is provided on the power supply side of the comparison potential generation circuit or control potential generation circuit, and this transistor is turned off during power down mode to prevent the supply of current. A nonvolatile semiconductor memory according to claim 1, characterized in that it is constructed as follows. 3. A patent characterized in that, as a means for controlling the conduction of a transistor equivalent to the memory cell, a plurality of transistors equivalent to the memory cell are provided, and the conduction of each of these transistors is controlled by a predetermined output. A nonvolatile semiconductor memory according to claim 1.