JPS6144352B2 - - Google Patents

Info

Publication number
JPS6144352B2
JPS6144352B2 JP56071614A JP7161481A JPS6144352B2 JP S6144352 B2 JPS6144352 B2 JP S6144352B2 JP 56071614 A JP56071614 A JP 56071614A JP 7161481 A JP7161481 A JP 7161481A JP S6144352 B2 JPS6144352 B2 JP S6144352B2
Authority
JP
Japan
Prior art keywords
memory
processor
pseudo
access
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56071614A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57187757A (en
Inventor
Hiroshi Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56071614A priority Critical patent/JPS57187757A/ja
Publication of JPS57187757A publication Critical patent/JPS57187757A/ja
Publication of JPS6144352B2 publication Critical patent/JPS6144352B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
JP56071614A 1981-05-13 1981-05-13 Data processing device Granted JPS57187757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56071614A JPS57187757A (en) 1981-05-13 1981-05-13 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56071614A JPS57187757A (en) 1981-05-13 1981-05-13 Data processing device

Publications (2)

Publication Number Publication Date
JPS57187757A JPS57187757A (en) 1982-11-18
JPS6144352B2 true JPS6144352B2 (enrdf_load_stackoverflow) 1986-10-02

Family

ID=13465693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56071614A Granted JPS57187757A (en) 1981-05-13 1981-05-13 Data processing device

Country Status (1)

Country Link
JP (1) JPS57187757A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS57187757A (en) 1982-11-18

Similar Documents

Publication Publication Date Title
US7051239B2 (en) Method and apparatus for efficiently implementing trace and/or logic analysis mechanisms on a processor chip
US6629268B1 (en) Method and apparatus for servicing a processing system through a test port
US7418526B2 (en) Memory hub and method for providing memory sequencing hints
JP2575557B2 (ja) スーパーコンピユータシステム
US5274648A (en) Memory card resident diagnostic testing
US3982111A (en) Memory diagnostic arrangement
JP2007508601A (ja) ハブベースの記憶システムにおけるダイレクトメモリアクセス用の装置および方法
JPH0223891B2 (enrdf_load_stackoverflow)
JP4132322B2 (ja) 記憶制御装置およびその制御方法
KR102478527B1 (ko) 이기종 메모리 시스템용 시그널링
JP2996440B2 (ja) データ処理システムの診断方式
JP2001006395A (ja) 半導体メモリ装置及びそのテストモード時の読出方法
JPH0690682B2 (ja) マルチプロセツサシステムの障害処理方式
CN114902197B (zh) 非易失性双列直插式存储器模块的命令重放
JP2559989B2 (ja) マルチプロセッサ・システムにおけるスペア・ビットをステアリングする装置および方法
US6643796B1 (en) Method and apparatus for providing cooperative fault recovery between a processor and a service processor
JP2001167005A (ja) メモリ診断方法とメモリ診断回路および半導体記憶装置
US7529890B1 (en) System, apparatus and method for facilitating on-chip testing
US6587963B1 (en) Method for performing hierarchical hang detection in a computer system
AU666625B2 (en) Scannable interface to non-scannable microprocessor
KR940002904B1 (ko) 데이타 처리 시스템 및 이 시스템에 있어서의 다수 메모리 어레이 테스팅 방법
JPS6144352B2 (enrdf_load_stackoverflow)
AU633898B2 (en) Method and means for interfacing a system control unit for a multi-processor system with the system main memory
Jone et al. An efficient BIST method for distributed small buffers
JP2947338B2 (ja) マルチプロセッサ・キャッシュ診断方法