JPS6142986B2 - - Google Patents

Info

Publication number
JPS6142986B2
JPS6142986B2 JP55053887A JP5388780A JPS6142986B2 JP S6142986 B2 JPS6142986 B2 JP S6142986B2 JP 55053887 A JP55053887 A JP 55053887A JP 5388780 A JP5388780 A JP 5388780A JP S6142986 B2 JPS6142986 B2 JP S6142986B2
Authority
JP
Japan
Prior art keywords
line
address
control memory
control
converting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55053887A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56149853A (en
Inventor
Masahito Hihara
Kyoshi Sato
Tatsuo Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5388780A priority Critical patent/JPS56149853A/ja
Publication of JPS56149853A publication Critical patent/JPS56149853A/ja
Publication of JPS6142986B2 publication Critical patent/JPS6142986B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
JP5388780A 1980-04-23 1980-04-23 Control memory access system of communication control unit Granted JPS56149853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5388780A JPS56149853A (en) 1980-04-23 1980-04-23 Control memory access system of communication control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5388780A JPS56149853A (en) 1980-04-23 1980-04-23 Control memory access system of communication control unit

Publications (2)

Publication Number Publication Date
JPS56149853A JPS56149853A (en) 1981-11-19
JPS6142986B2 true JPS6142986B2 (en, 2012) 1986-09-25

Family

ID=12955233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5388780A Granted JPS56149853A (en) 1980-04-23 1980-04-23 Control memory access system of communication control unit

Country Status (1)

Country Link
JP (1) JPS56149853A (en, 2012)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0616638B2 (ja) * 1982-10-04 1994-03-02 株式会社日立製作所 通信制御処理装置の制御方式
JPS59108140A (ja) * 1982-12-14 1984-06-22 Fujitsu Ltd 回線アドレス変換方式

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603659B2 (ja) * 1977-10-24 1985-01-30 富士通株式会社 データ伝送処理システム

Also Published As

Publication number Publication date
JPS56149853A (en) 1981-11-19

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