JPS56149853A - Control memory access system of communication control unit - Google Patents

Control memory access system of communication control unit

Info

Publication number
JPS56149853A
JPS56149853A JP5388780A JP5388780A JPS56149853A JP S56149853 A JPS56149853 A JP S56149853A JP 5388780 A JP5388780 A JP 5388780A JP 5388780 A JP5388780 A JP 5388780A JP S56149853 A JPS56149853 A JP S56149853A
Authority
JP
Japan
Prior art keywords
address
control unit
control memory
communication control
ineffective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5388780A
Other languages
Japanese (ja)
Other versions
JPS6142986B2 (en
Inventor
Masahito Hihara
Kiyoshi Sato
Tatsuo Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5388780A priority Critical patent/JPS56149853A/en
Publication of JPS56149853A publication Critical patent/JPS56149853A/en
Publication of JPS6142986B2 publication Critical patent/JPS6142986B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To exactly check a device address which is issued to a communication control unit from a central processing unit, by accessing the control area of a subchannel control memory and a circuit control memory, etc. in accordance with an internal address. CONSTITUTION:When a command is issued from the central processing unit 1, the communication control unit 2 prepares its address from the device address which has been set to the device address register 3, refers to the conversion table 4, derives the internal address, and holds it in the internal address register 7. When the indexed internal address is effective, the internal address is used as an address of the subchannel control memory 8. When an ineffective code is indexed, the device address concerned is ineffective, therefore, it is reported to the central processing unit that said address is ineffective.
JP5388780A 1980-04-23 1980-04-23 Control memory access system of communication control unit Granted JPS56149853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5388780A JPS56149853A (en) 1980-04-23 1980-04-23 Control memory access system of communication control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5388780A JPS56149853A (en) 1980-04-23 1980-04-23 Control memory access system of communication control unit

Publications (2)

Publication Number Publication Date
JPS56149853A true JPS56149853A (en) 1981-11-19
JPS6142986B2 JPS6142986B2 (en) 1986-09-25

Family

ID=12955233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5388780A Granted JPS56149853A (en) 1980-04-23 1980-04-23 Control memory access system of communication control unit

Country Status (1)

Country Link
JP (1) JPS56149853A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963836A (en) * 1982-10-04 1984-04-11 Hitachi Ltd Method for controlling processor of communication control
JPS59108140A (en) * 1982-12-14 1984-06-22 Fujitsu Ltd Method for converting address of circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5460536A (en) * 1977-10-24 1979-05-16 Fujitsu Ltd Process system for data transmission

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5460536A (en) * 1977-10-24 1979-05-16 Fujitsu Ltd Process system for data transmission

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963836A (en) * 1982-10-04 1984-04-11 Hitachi Ltd Method for controlling processor of communication control
JPS59108140A (en) * 1982-12-14 1984-06-22 Fujitsu Ltd Method for converting address of circuit
JPH0129338B2 (en) * 1982-12-14 1989-06-09 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6142986B2 (en) 1986-09-25

Similar Documents

Publication Publication Date Title
JPS56140452A (en) Memory protection system
JPS5242334A (en) Computer
JPS56149853A (en) Control memory access system of communication control unit
JPS53139939A (en) Memory addressing method
JPS53102635A (en) Access system for memory unit
JPS5440049A (en) Information process system
JPS5611584A (en) Error check system for character pattern
JPS5319738A (en) Processing unit stop control system
JPS5729145A (en) Formation of code table
JPS5215241A (en) Bus test control system for data processing system
JPS5423335A (en) Page detection mechanism
JPS531779A (en) Portable input unit for numerical control system
JPS5380932A (en) Input/output control unit
JPS5563423A (en) Data transfer system
JPS548428A (en) Address buffer circuit
JPS5769343A (en) Paging system of microcomputer
JPS5434728A (en) Input/output control system
JPS5759220A (en) Data transfer system
JPS5386534A (en) Address check process system
JPS5235529A (en) Calculator address control device
JPS5335435A (en) Automatic tlb erase and processing unit
JPS5696356A (en) Multimicroprocessor
JPS5335436A (en) Data processing unit having address converting functions
JPS53129931A (en) Control system for magnetic bubble memory device
JPS52112237A (en) Memory control unit