JPS54131838A - Channel device - Google Patents

Channel device

Info

Publication number
JPS54131838A
JPS54131838A JP3924378A JP3924378A JPS54131838A JP S54131838 A JPS54131838 A JP S54131838A JP 3924378 A JP3924378 A JP 3924378A JP 3924378 A JP3924378 A JP 3924378A JP S54131838 A JPS54131838 A JP S54131838A
Authority
JP
Japan
Prior art keywords
bits
address
subchannel
conversion
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3924378A
Other languages
Japanese (ja)
Inventor
Masao Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3924378A priority Critical patent/JPS54131838A/en
Publication of JPS54131838A publication Critical patent/JPS54131838A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure the operation of I/O as the using unit via an optional combination within the range of the subchannel by providing the address conversion table to secure conversion of the device address of I/O into the corresponding subchannel address.
CONSTITUTION: Device address DA7 of the channel control word is composed of 8 bits. And the upper 4 bits give positioning to address conversion table 8, and the lower 4 bits are loaded to the lower 4 bits of memory address register 9. At the same time, the pattern of upper 4 bits of DA corresponded to the upper 4 bits of address SA of subchannel 2 is set previously to table 8 via operation panel 10. Thus, the conversion is carried out between DA and SA, and the upper 4 bits of SA obtained through conversion are loaded to the upper 4 bits of register 9. As a result, SA can be obtained to give an access to subchannel 2 for register 9.
COPYRIGHT: (C)1979,JPO&Japio
JP3924378A 1978-04-05 1978-04-05 Channel device Pending JPS54131838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3924378A JPS54131838A (en) 1978-04-05 1978-04-05 Channel device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3924378A JPS54131838A (en) 1978-04-05 1978-04-05 Channel device

Publications (1)

Publication Number Publication Date
JPS54131838A true JPS54131838A (en) 1979-10-13

Family

ID=12547679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3924378A Pending JPS54131838A (en) 1978-04-05 1978-04-05 Channel device

Country Status (1)

Country Link
JP (1) JPS54131838A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60108951A (en) * 1983-11-17 1985-06-14 Fujitsu Ltd Data chaining system
JPS60142455A (en) * 1983-12-29 1985-07-27 Fujitsu Ltd Index processing system of routine table
JPS60150152A (en) * 1984-01-17 1985-08-07 Fujitsu Ltd Channel control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60108951A (en) * 1983-11-17 1985-06-14 Fujitsu Ltd Data chaining system
JPH0122939B2 (en) * 1983-11-17 1989-04-28 Fujitsu Ltd
JPS60142455A (en) * 1983-12-29 1985-07-27 Fujitsu Ltd Index processing system of routine table
JPS60150152A (en) * 1984-01-17 1985-08-07 Fujitsu Ltd Channel control system

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