JPS60108951A - Data chaining system - Google Patents

Abstract

PURPOSE:To utilize effectively resources and to suppress the increase of the number of hardwares at its minimum by forming chaining registers at the rate of 1:1 to subchannels and allowing respective subchannels to use optional registers under time division. CONSTITUTION:The chaining registers 11-0, 11-1 are formed at the rate of 1:1 to the subchannels of a computer system and data a, b to copied to a transfer control register 14 are set up respective registers 11-0, 11-1. In addition, valid bits V0, V1 and identification codes IDo, ID1 are included in the registers 11-0, 11-1. The bits V0, V1 indicate the validity of the contents of the registers 11-0, 11-1 and the identification codes ID0, ID1 indicate the subchannels corresponding to the contents of the registers 11-0, 11-1. The Nos. ''0'', ''1'' of the subchannels executing transfer and chaining and the data (a), (b) are processed by comparators 12-0, 12-1 and a multiplexer 13. Thus, the registers 11-0, 11-1 are used under time division and the increment of the number of hardwares is suppressed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides chaining registers whose number is smaller than the number of subchannels, and adds information identifying the subchannel that uses the register to the chaining register. The present invention relates to a data chaining method in which a plurality of subchannels share a chaining register and any register can be used in a time-sharing manner.

[Conventional technology and problems]

FIG. 1 is a diagram showing an example of the configuration of a computer system. 1st
In the figure, 1 is a main processing unit, 2 is a main memory, 3 is a subchannel, 4 is a channel, 5 is a chaining register,
6 is a transfer control register, 7 is an address update circuit, 8 is a byte count update circuit, 9 and 10 are multiplexers, 51 and 61 are address registers, 52 and 62 are byte count registers, 53 and 63 are status - Registers 54 and 64 indicate mode registers.

When processing multiple areas on the main memory in one input/output operation, there are two methods for starting data transfer for the next area after data transfer for one area is completed.

The first method is to retrieve the next channel command when the data transfer for one area is completed, analyze the command, reset the transfer control register in the subchannel, and restart the data transfer. be. Here, the transfer control registers include an address register that indicates the main memory address where data is transferred, a byte count register that indicates the number of bytes transferred, a mode register that indicates the transfer mode, and a status register that holds errors and other errors. status/
It is a general term that includes registers, etc., and is distinguished from chaining registers.

The second method, as shown in FIG. 1, is to provide a chaining register 5 separately from the subchannel internal pressure transfer control register 6, and to take out the next channel command while data transfer of one area is being executed. Information for controlling the next data transfer is set in the chaining register 5. When the data transfer of the area being executed is completed, the data is copied from the chaining register 5 to the transfer control register 6 and the transfer is continued.

However, in the first method, chaining takes time, and if waiting is not allowed because a high-speed disk device is used as the input/output device, an overrun may occur. In addition, the latter second method solves the above-mentioned problems in the first method, but when trying to chain all subchannels, the registers become There is a problem in that the amount of hardware required is twice that of method 1.

[Purpose of the invention]

The present invention is based on the above considerations, and provides a data chaining method that allows chaining registers to be shared by multiple subchannels, thereby minimizing the increase in hardware. The purpose is to

[Invention Q configuration]

To this end, the data chain method of the present invention uses a plurality of input/output subchannels and a plurality of areas for storing control information and an area to perform the next input/output operation in order to perform input/output operations between the plurality of input/output subchannels and the plurality of areas of the main memory. A data chain method in a computer system, which has registers, and upon detecting the end of an input/output operation in an area being executed, retrieves information from the register and continues the input/output operation, comprising:
An identification code indicating which subchannel information is stored is added to each of the registers, so that each of the registers can be shared by the plurality of input/output subchannels. be.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the configuration of one embodiment of the present invention.

In FIG. 2, 11-0 and 11-1 are chaining registers, 12-0 and 12-1 are comparison circuits, 13 is a multiplexer, and 14 is a transfer control register.

In the example shown in FIG. 2, the number of subchannels is four, and there are two chaining registers 1-0 and 11-1. Chaining register 1l-0 (!:11-1 is
Concerning the information and status to be copied to the transfer control register 14, in addition to the information that saves the status in the transfer control register 14, valid
Bits ■, η, and identification code IDo related to the present invention,
It has ID+. The valid ° bit vo%V indicates the validity of the contents of the chaining registers 11-0 and 11-1, and indicates the validity of the contents of the chaining registers 11-0 and 11-1.
It is set (enabled) when the value is set, and is reset (invalidated) when chaining ends. This prevents data that has been used once from being used again, and also allows you to identify whether or not it is in use when assigning a chaining register to a subchannel.Identification Code I Do% ID , indicates for which subchannel the contents of the chaining registers 11-0 and 11-1 are prepared.

In FIG. 2, #0 chaining register 1l-
OK assumes that there is (valid) data for the #0 subchannel and that the #1 chaining register 11-1 has (valid) data for the #2 subchannel.

Therefore, when data transfer is performed on subchannel #2, if the byte counter in the transfer control register 14 indicates the number of remaining transfer bytes = 0, specify the data chain using the mode register. In some cases chaining is performed. At this time, the number of the subchannel where the chaining request occurred, in this case, the binary vlov, and the identification code I of each chaining register 11-0.11-1.
D, . . . ID, are compared by the comparison circuit 12-0.12-1. The result is ID. is a mismatch, ID.

Since they match, the output of comparator circuit 12-1
The contents of the chaining register 11-1 are selected by the multiplexer 13 and copied to the transfer control register (#2) of the request source subchannel.

However, when comparing identification codes, the valid bit is WQ.
If it is W, the comparator circuit 12-0.12-1 considers it to be a mismatch regardless of the content of the identification code.

Furthermore, if an identification code that matches the requesting subchannel is not found, or if the identification codes of two or more chaining registers match, a chaining error occurs. In this case, the channel either reads the next command and resets the transfer control register to restart the data transfer, or uses the 0° data chain function to report the error to the main processing unit and terminate the data transfer. When there are multiple subchannels with multiple subchannels, the probability that all of them will execute the data chain at the same time is small, or when there are several channels that are allowed to wait for input/output when executing the data chain, The number of chaining registers to be used may be smaller than the number of subchannels. Therefore, the present invention provides an arbitrary number of chaining registers smaller than the number of subchannels, and adds information to the chaining registers to identify the subchannel that uses the chaining registers. Multiple subchannels share chaining registers,
This allows arbitrary chaining registers to be used in a time-sharing manner.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, each subchannel uses arbitrary chaining registers in a time-sharing manner, without providing subchannels and one-to-one IK chaining registers, thereby making resources effective. You can plan to use it. Moreover, any number of chaining registers may be provided in accordance with the required performance of the system, regardless of the number of subchannels, and the increase in hardware can be kept to a minimum.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a computer system, and FIG. 2 is a diagram showing the configuration of one embodiment of the present invention. 1... Main processing unit, 2... Main memory, 3... Sub channel, 4 river channels, 5. 11-o and 11-1...
Chaining registers, 6 and 14...Transfer control registers, 7--address update circuit, byte count update circuit, 9.1o and 13...Multiplexer, 12-0 and 12-1 Comparison circuits, 51 and 61 address registers, 52 and 62 byte count registers, 53 and 63... status registers, 54 and 6
4...Mode register. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (1)

[Claims] It has multiple input/output subchannels and multiple registers to store control information and the area where the next input/output operation is to be performed in order to perform input/output operations with multiple areas of main memory, and is currently being executed. A data chain method in a computer system in which when the end of an input/output operation of an area is detected, information is retrieved from the register and the input/output operation continues. A data chain method characterized in that an identification code indicating whether information is stored is added so that each of the registers can be shared by the plurality of input/output subchannels.