JPS6141477B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color solid-state imaging device using a CCD (charge-coupled device) having a color filter.
In particular, we are developing a new solid-state imaging device in which the amount of charge accumulation can be controlled independently for each pixel corresponding to each color of the solid-state imaging device, and the element itself has a gain adjustment function, a gamma correction function, etc. This is what we provide.

Hereinafter, a solid-state imaging device according to the present invention will be explained using the drawings.

FIG. 1 is a schematic diagram of an embodiment in which the present invention is applied to an interline shift type color solid-state imaging device. In FIG. 1, 1 is according to the present invention.
A CCD solid-state image sensor, 2 indicates a color filter arranged on the light-receiving surface side of this solid-state image sensor. The color filter 2 is, for example, a so-called striped color filter in which three primary colors of red (R), blue (B), and green (G) are sequentially and repeatedly arranged in a stripe shape, and black (Bl) is arranged at the final end. The solid-state image sensor 1 includes a sensor section 3 having a plurality of light receiving sections serving as picture elements and a vertical shift register, and a horizontal shift register 4 provided on the output side of each vertical shift register. A plurality of light receiving sections are arranged, for example, in a matrix, and a vertical shift register is arranged on each side of the light receiving sections. In the figure, an area having one row of light receiving sections arranged vertically and a vertical shift register on one side is referred to as one pixel example 5, and this pixel row 5 corresponds to each color (R), ( G),
A large number of them are arranged corresponding to (B) and (Bl). In the present invention, in particular, in the sensor section, the amount of charge accumulated in the light receiving section is controlled independently for each pixel corresponding to each color of the color filter 2, that is, for each pixel row 5 in the illustrated example. A charge accumulation control gate section 6 is provided, and independent charge accumulation control pulses φr, φb, φg are applied to each control electrode 7R, 7B, 7G of the charge accumulation control gate section 6, respectively. The charge accumulation control gate section 6 uses a gate section of an overflow drain region to flow excess charge generated in the light receiving section, and the control electrodes of the control gate section are separated and independently for each pixel column corresponding to each color. The independent control electrodes 7R, 7B, 7G are commonly connected for each color, and the control pulses φr, φ
Connect to terminals T ₁ , T ₂ and T ₃ provided with terminals b and φg. Note that the control electrode 7K of the picture element column corresponding to black (Bl) of the color filter 2 receives which control pulse φ
r, φb or φg may be given. In this example, the control electrode 7K is connected to the terminal _T1 .

According to such a configuration, the terminals T ₁ , T ₂ and T ₃
When required control pulses φr, φb, and φg are applied to the respective control electrodes 7R, 7B, and 7G through Changes according to the control pulse voltage,
By controlling the surplus charge flowing from the light receiving portion to the overflow drain region, the amount of accumulated charge under the light receiving portion of each pixel column corresponding to each color is controlled independently for each color.

For this reason, for example, each color (R), (B)
By simultaneously controlling the charge accumulation control gate section 6 in each pixel row 5 corresponding to (R) and (G), automatic gain control or automatic aperture function can be provided. ) and (G) respectively, it is possible to provide a so-called white balance adjustment function, and furthermore, the control signal given to the charge accumulation control gate section 6 can be controlled with non-linearity. By providing this, gamma correction is also possible, and sensitivity adjustment, white balance adjustment, and even gamma-corrected color imaging output can be obtained from the solid-state imaging device 1.

Therefore, according to this color solid-state imaging device,
Color temperature conversion filters or automatic apertures are no longer required, and automatic gain control circuits, gamma correction circuits, etc. can be omitted in the signal processing circuit of the phase separation method, and automatic white balance adjustment is also easy, simplifying the signal processing circuit. can be achieved. Furthermore, the tolerance for variations in the transmission characteristics of each color of the color filter is increased.
Furthermore, color reproduction is also improved.

2 to 5 show an example of a specific structure of the solid-state imaging device shown in FIG. 1, in which FIG. 2 is a plan view, FIG. The figure is a cross-sectional view taken along the line BB, and FIG. 5 is a cross-sectional view of the main part for explaining the operation. In FIG. 2, the shaded area 10 is a channel stopper area, and the area indicated by broken lines is a light receiving part 11 that becomes a picture element, and the light receiving part 11R ₁ corresponds to red (R) of the stripe color filter 2. , 11R ₂ columns,
A row of light receiving sections 11B ₁ and 11B ₂ corresponding to blue (B) and light receiving sections 44G ₁ and 11G ₂ corresponding to green (G)
rows are repeatedly arranged in sequence along the horizontal direction,
A vertical shift register 12 is arranged on one side of each column of light receiving sections 11, respectively. On the other side of each row of light receiving sections 11, an overflow drain region 13 is provided adjacent thereto, and a gate region between each overflow drain region 13 and the light receiving section 11, that is, a charge accumulation control gate section 6 is provided. The surplus charge generated in the portion 11 is flowed into the overflow drain region 13 through each control gate portion 6.

These include a channel stopper region 10, a light receiving section 11, a vertical shift register 12, an overflow drain region 13, and a charge accumulation control gate section 6.
are formed on a common semiconductor substrate, for example, a P-type silicon semiconductor substrate 14, as shown in FIGS. 3 and 4. The light receiving section 11 is constructed by depositing a transparent electrode, that is, a sensor electrode 16, on a base 14 through an insulating layer, for example, a SiO ₂ layer 15a, having a predetermined thickness.
Here, it is possible to connect the sensor electrodes 16 of each light receiving section in common, but in the case of interlacing, the light receiving sections 11B ₁ , 11B 1 , 11B ₁ of the first field,
44G ₁ and second field light receiving section 11R ₂ , 11
Between B ₂ and 11G ₂ , the light reception time is half a cycle (1/6
Since there is a difference of 0 seconds), if the sensor electrode 16 is made common across the entire surface, the sensitivity will be halved. For this reason, it is desirable to provide the sensor electrodes 16 separately for the light receiving portions corresponding to the first field and the second field.

On the other hand, the vertical shift register section 12 has a number of transfer sections corresponding to the respective light receiving sections 11, and is configured such that signal charges are transferred in the direction a of the arrow by, for example, two-phase clock pulses φ _V1 and φ _V2 . It is something that
Each transfer section has a transfer gate area and a storage gate area. That is, the transfer section to which clock pulse φ _V1 is applied has a transfer gate region φ ₁ T and storage gate region φ ₁ S, and the transfer section to which clock pulse φ _V2 is applied has a transfer gate region φ ₂ T and a storage gate region. φ ₂ S.

The storage gate regions φ ₁ S and φ ₂ S are each formed with a thin insulating layer, e.g., SiO ₂ layer 15b, under the electrode, and the transfer gate regions φ ₂ T and φ ₂ T are each formed with an insulating layer, e.g., SgiO _{2 ,} under the electrode. The layer 15c is formed thicker than the storage gate regions φ ₂ S and φ ₂ S, and the common clock pulse φ _V1 = “1” or φ _V2
As shown by reference numeral 17 when ="1" is applied, the potential well under the storage gate region φ ₁ S or φ ₂ S becomes the transfer gate region φ ₁ T.
Or it is made to be deeper than the potential well under φ ₂ T (see Figure 4).

Between each storage gate region φ ₁ S and the light receiving section 11, the accumulated charges are transferred from the light receiving section 11 to the clock pulse φ _V1.
Alternatively, gate regions ST ₁ and ST ₂ for transferring to the vertical soft register section 12 by φ _V2 are provided.

Note that the storage gate region φ ₁ S, the transfer gate region φ ₁ T, and the electrode 18 of the gate region ST ₁
S, 18T and 20a are commonly connected, and storage gate region φ ₂ S and transfer gate region φ
₂ T and electrodes 19S, 19T and 2 of gate region ST ₂
0b are commonly connected. Also gate areas ST ₁ and ST ₂
The electrodes 20a, 20b are the electrodes 18S, 18T, 1
It is also possible to apply a potential independently without connecting to 9S and 19T.

The channel stopper region 10 is formed by a high concentration region of the same conductivity type as the substrate 14. 21 is an insulating layer 2 such as SiO ₂ on the surface of the other parts except for the light receiving part 11.
This is a light-shielding layer deposited through 2.

On the other hand, the overflow drain region 13 is formed by a semiconductor region having a conductivity opposite to that of the base body 14, and the charge storage control gate portion 6 is formed by forming a control electrode on the base body through an insulating layer 15d having a predetermined thickness, such as a SiO ₂ layer. 7 [7R, 7B, 7G, 7K] are deposited and formed. In this case, each control electrode 7R, 7B, 7G and 7K of the control gate section 6 corresponding to each color is formed independently, and each control electrode 7R, 7B, 7K is formed independently.
G are connected to terminals T ₁ , T ₂ and T ₃ respectively.

Next, the operation of this configuration will be explained. Here, interlacing is performed. First, when a predetermined positive electrode φ _S = "1" is applied to the sensor electrode 16 through the terminal T _S during the light receiving period, a deep ponsial well 23 is formed under the sensor electrode 16 and the well 23 is adjusted according to the amount of light received. Minority carriers 24 are accumulated. Next, when φ _S =“0” is applied to the sensor electrode 16, and clock pulses φ _V1 = “1” and φ _V2 = “0” are applied to the vertical shift register section 12 through terminals T _A and T _B , respectively. Each light receiving portion 11R ₁ , 11B ₁ , 11 is formed with a ponsial well shown by a solid line 17 and corresponds to the picture element of the first field.
The accumulated charge 24 of G ₁ is transferred to each corresponding storage gate region φ ₁ S of the vertical shift register through the gate region ST ₁ , respectively, and then clock pulses φ _S1 and φ are applied to the vertical shift register 12 through terminals T _A and T _{B. V2} to the horizontal shift register section 4, and the red (R), blue (B), green ( G) signal charge, that is, a point sequential signal can be extracted. Next, in the second field, the receiving parts 11R ₂ ,
The accumulated charges at 11B ₂ and 11G ₂ are the voltage φ _S of the sensor electrode 16 = “0”, the clock pulse of the vertical shift register φ _V1 = “0”, and φ _V2 = “1”.
are transferred to the vertical shift register section 12 through the gate region _ST2 , respectively, and in the same way as above, from the output terminal t of the horizontal shift register section 4
Red (R) for each horizontal line corresponding to the field,
Blue (B) and green (G) dot sequential signals are extracted.
Here, if the sensor electrode 16 is provided separately for the receiving parts corresponding to the first field and the second field as described above, the sensor electrode of the first field and the sensor electrode of the second field On the other hand, the sensor electrodes φ _S are applied alternately every one field time.

On the other hand, each control electrode 7 of each charge storage control gate section 6 adjacent to the overflow drain region 13
Terminals T ₁ , T ₂ , T ₃ for [7R, 7B, 7G]
A predetermined charge accumulation control pulse φ is applied independently through each
When r, φb, and φg are given, the height of the potential barrier 25 formed under each control electrode 7 becomes equal to the height of the control pulses φr, φb, and φg, as shown by symbols h ₁ and h ₂ in FIG. 5, respectively. The amount of charge that changes depending on the voltage and is stored in the potential well 23 under the sensor electrode 16 is controlled. Therefore, for example AGC
If control pulses φr, φb, and φg from the storage control unit based on the control signal, white balance control signal, and signal corresponding to the gamma value are applied to each control electrode 7, the amount of accumulated charge in each light receiving unit is adjusted accordingly. Under the control, color video outputs with sensitivity adjustment, white balance adjustment, and gamma correction are obtained from terminal t of the horizontal shift register.

6 and 7 show other examples of the present invention, FIG. 6 is a plan view showing the pattern of the light receiving section and its charge accumulation control electrode 7 corresponding to each color, and FIG. 7 is a plan view showing the pattern of the charge accumulation control electrode 7. FIG. 3 is a plan view showing the arrangement of a light receiving section, a vertical shift register, an overflow drain region, etc., excluding electrodes.

In addition, in Figures 6 and 7, Figures 1 to 5
Parts corresponding to those in the figure are designated by the same reference numerals.

In FIG. 7, the lined area 10 is the channel stopper area, and the diagonally lined area is the light-receiving area 11 that becomes the picture element, and these are the red, blue, and green colors of the mosaic color filter. The light receiving sections 11R, 11B, and 11G corresponding to the above are arranged in a so-called checkered pattern, with two of them forming a set. A vertical shift register 12 is provided at one end of each column of the light receiving section 11, respectively.
An island-shaped overflow drain region 13 is formed in the space between the vertical light-receiving portions created by the checkered pixel arrangement. Each light receiving section 1
1R, 11B, and 11G are constructed by depositing a transparent electrode, that is, a sensor electrode, on a semiconductor substrate through an insulating layer of a predetermined thickness, for example, a SiO ₂ layer, and in this case,
The sensor electrodes of each of the light receiving sections 11R, 11B, and 11G are commonly connected so that a common sensor voltage φ _S is applied thereto.

The vertical shift register 12 has transfer sections of the number of bits corresponding to the number of light receiving sections 11R, _11B , and _11G for each column. The carrier is transferred, and each transfer section has a first transfer section to which a clock pulse φ _V1 is applied, and a second transfer section to which a clock pulse φ _V2 is applied.
The second transfer section includes a transfer gate area and a storage gate area. That is, in the first transfer section, the transfer gate region φ
₁ T and storage gate region φ ₁ S, and the second
The transfer section includes a transfer gate region φ ₂ T and a storage gate region φ ₂ S. The first transfer section and the second transfer section in each vertical shift register 12 are arranged in a zigzag pattern with respect to a vertical line, and the storage gate region φ ₁ S of each first transfer section and each light receiving section 11 are separated by 1 bit from each other.
A gate region _ST1 is provided between the light receiving sections 11R, 11B, and 11G, and by one transfer clock pulse _φV1 , the accumulated charge in each light receiving section 11R, 11B, and 11G is transferred to the storage of the first transfer section through the gate region _ST1. The signal is transferred to the gate region φ ₁ S. The electrodes 18S, 18T of the first transfer section and the electrodes 19S, 19T of the second transfer section are formed parallel to the charge transfer direction a for each column, and the electrodes of the first transfer section and the electrodes of the second transfer section are commonly connected to each other, from which terminals T _A and T _B are led out.

On the other hand, a control gate section 6 for controlling accumulated charge is provided between the overflow drain region 13 and both of the light receiving sections 11 adjacent to each other in the vertical direction, and the control gate section 6 of each light section 11R, 11B, and 11G corresponding to each color is provided. The control electrodes 7R, 7B and 7G of the section are connected in common in the horizontal direction as shown in FIG.
They are connected to terminals T ₁ , T ₂ , and T ₃ , respectively.

The operation of this element is such that a sensor voltage φ _S =“1” is applied to the sensor electrode 16 during the light receiving period, so that charges corresponding to the amount of light received are accumulated in each light receiving portion 11R, 11B, and 11G, and then By setting φ _S = “0” and clock pulses φ _V1 = “1” and φ _V2 = “0” applied through the terminals T _A and T _B , all the light receiving parts _11R , 1 are connected through the gate region ST1.
The accumulated charges of 1B and 11G are transferred to the corresponding storage gate regions φ ₁ S of the vertical shift register section 12, and then sequentially transferred to the horizontal shift register section by clock pulses φ _V1 and φ _V2 .

On the other hand, when predetermined charge accumulation control pulses φr, φb, φg are applied independently to each charge accumulation control electrode 7R, 7G, 7B through terminals T ₁ , T ₂ , T ₃ ,
The height of the potential barrier under the control gate section 6 adjacent to each light receiving section 11R, 11B, 11G is changed to control the accumulated charges in the light receiving section 11R, 11B, 11G for each color. Therefore, even in this configuration, the functions of sensitivity adjustment, white balance adjustment, and gamma correction can be provided by controlling the control pulses for each independent control electrode 7R, 7B, and 7C, and the functions of sensitivity adjustment, white balance adjustment, and gamma correction can be provided. It has similar effects.

As described above, according to the present invention, the electrode of the gate portion adjacent to the overflow drain region is divided into picture elements corresponding to each color, and a charge accumulation control pulse is applied to each electrode independently to cause the accumulation of picture elements of each color. By controlling the amount of charge, it is possible to adjust the gain independently for each color, simplifying subsequent signal processing,
This has great practical benefits, such as the omission of color temperature conversion filters and ND (neutral density) filters.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an example of a solid-state imaging device according to the present invention, FIG. 2 is a plan view showing a specific configuration of the present invention, FIG. 3 is a sectional view taken along line A-A, and FIG. 5 is a sectional view of the main part thereof, FIG. 6 is a plan view showing each light receiving part and a charge accumulation control electrode pattern showing another example of the present invention, and FIG. 7 is a diagram showing the charge accumulation control electrode pattern. FIG. 3 is a plan view with storage control electrodes removed. 1 is a solid-state imaging device, 2 is a color filter, 3 is a sensor section, 4 is a horizontal shift register section, 6 is a charge accumulation control gate section, 7R, 7B, 7G, 7K are control electrodes, 11R, 11B, 11G are light receiving sections , 13
is the overflow drain region.

Claims (1)

[Claims] 1 In a solid-state imaging device with a color filter,
A control gate section is provided between each picture element and an adjacent overflow drain region, and an independent control potential is applied to each of the control gate sections of the picture element corresponding to each color of the color filter. Solid-state imaging device.