JPH03187591A - Driving method for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To prevent the generation of flicker at the time of interlace-driving the solid-state image pickup element of a frame transfer type attached with a mosaic-shaped color separation filter by outputting a balanced color component signal in an even field and an odd field. CONSTITUTION:In interlace-driving, since the potential of a transfer electrode during the transfer period of photoelectric charge becomes equal in the even field EVEN and the odd field ODD, and the accumulation of the photoelectric charge in both the fields is executed under the state of the same potential, difference between the video signals of both the fields is eliminated. Besides, since the photoelectric charge accumulated for every picture element is transferred successively after the portion of two picture elements is mixed once as making transfer clock phi2 or phi4 high potential, the unnecessary mixing of the photoelectric charge due to the phase shift of the transfer clocks phi1 to phi4 is prevented. Thus, the solid state image pickup element of a frame transfer system attached with the mosaic filter can be interlace-driven without causing the flicker.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for driving a frame transfer type solid-state image sensor equipped with a mosaic color separation filter, and in particular to a method for preventing flicker during interlaced driving. Regarding.

(Existence) Conventional technology In single-chip color imaging devices, color separation filters in mosaic, stripe, etc. are attached to the light-receiving surface of the CCD solid-state image sensor mounted on the imaging device. Pixels are associated with each color component. Although using a mosaic color separation filter provides higher horizontal resolution than using a stripe color separation filter, the C
Since there is a problem that the processing of the video signal output from the CD becomes complicated, a color separation filter is selected depending on the purpose of use of the imaging device.

FIG. 3 is a plan view showing the light surface of a frame transfer type CCDCC solid-state image sensor equipped with a mosaic color separation filter.

A plurality of channel regions (1) are separated from each other by channel separation regions (2) and extend in the vertical direction on the light receiving surface of the CCD. Then, two-layer transfer electrodes (3) and (4) are formed perpendicularly to the channel region (1) with an insulating film interposed therebetween. In addition, the upper layer side transfer electrode (4) is formed with a narrow width on the channel separation region (2>), and an opening is formed between it and the transfer electrode (3) to improve light receiving efficiency. For example, a four-phase transfer clock is applied to these transfer electrodes (3) and (4), and information charges generated in the channel region (1) are transferred along the channel region (1).

A mosaic color separation filter (10
) is divided according to the pixels on the light-receiving surface, and each divided area has yellow (Ye), cyan (Cy), and gnome (G).
) and white (w) are given in a predetermined order. Pixels on the light-receiving surface are vertically separated by a channel separation region (2) and are separated by transfer electrodes (3) and (4).
are separated horizontally by a potential barrier formed by That is, the vicinity of the ends of the transfer electrodes (3) and (4) become the boundaries of each pixel, and the width of the pair of transfer electrodes (3 and 4) corresponds to one pixel. Therefore, the color separation filter (10) is
Vertically divided along the channel separation region (2) and transferred it! 1 (3) (4) horizontally along the edges.

In such a COD, interlaced driving is usually adopted in which two pixels in the vertical direction are simultaneously read out and the combination is reversed for each field, thereby improving the resolution. That is, in an odd field, the pixels in the n-th row and the n+1-th row are read out simultaneously, and in the even-numbered field, the pixels in the n-1th row and the n-th row are read out simultaneously. . A luminance signal is obtained from the sum of horizontally adjacent signals read out from the CCD, and a color component signal is obtained from the difference.

FIG. 4 is a timing diagram when performing interlaced driving as described above, and FIG. 5 is a diagram showing the potential state at each timing, and shows the XY cross section of FIG. 3.

In the even field EVEN, the transfer clocks φ1 to φ3 are fixed at a high potential and the transfer clock φ4 is fixed at a low potential during the photocharge accumulation period, and as shown in TI in FIG. 5, the potential barrier formed by the transfer clock φ4 Photocharges of the respective color components of W and Ye, W and Cy are mixed and accumulated in potential wells separated for each pixel and formed by transfer clocks φ, to φ. Then, at the end of the accumulation period, the transfer clock φ becomes low level, and as shown at T in FIG. 2, the potential well formed by the transfer clock φ1 disappears, and the potential well formed by the transfer clocks φ, φ A photocharge is transferred to a potential well. After this, the transfer clock is set to φ4. φ1. φ2. φ is repeatedly set to a high potential in the order of φ□φ8 . Photocharges are transferred by four-phase driving in which the potential is lowered in the order of φ4°φ. Therefore, color component signals W+ Ye and 'd+ Cy are repeatedly obtained. In addition, in the adjacent channel region (1), G and cy, c and Ye are mixed and the color component signal G+C
y, G+Ye are obtained.

On the other hand, in the odd field ODD, φ, φ, φ4 are fixed at a high potential and the transfer clock φ is fixed at a low potential during the photocharge transfer period, and the transfer clock φ is formed as shown in T in FIG. The photocharges of the W+Ye and W+Cy (7) color components are accumulated in potential wells formed by transfer clocks φ1φ and φ4, which are separated every two pixels by a potential barrier. When the accumulation period ends, the transfer clock φ,
becomes low level, and then transfer clocks φ1 to φ4 of 4
Photocharge is output by phase drive. In this odd field ODD, the combination of pixels to be mixed is reversed to that in the even field EYEN, and by combining the video signal obtained in the even field EVEN and the video signal obtained in the odd field ODD, one frame is obtained. is configured.

The video signal obtained in the above manner is (W+Ye)+(
Luminance signal from (Cy+G), (w+ye) −(Cy+
c) Or obtain a color signal from ($J+Cy)-(Ye+c). That is, W=R+G+B, Ye=R+G, C
Since y=G+B (R: red, B nibble), the luminance signal is 4f2R+4c+2B, and the color signal is 2R or 2B, respectively.

(8) Problems to be Solved by the Invention However, when performing interlaced driving as described above, the potential of each transfer electrode (3) (4) during the photocharge accumulation period is different between even field EVEN and odd field ODD. In contrast, the lack of symmetry between the transfer clocks φ and φ4 causes a slight difference between the color component signals obtained from both fields, and this difference causes a problem that appears as flicker on the reproduced screen.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to prevent flicker from occurring when a frame transfer type solid-state image pickup device equipped with a mosaic color separation filter is interlace driven.

(2) Means for solving the problems The present invention has been made to solve the above problems,
A plurality of channel regions partitioned by separation regions and arranged parallel to each other to accumulate and transfer photocharges generated by photoelectric conversion, and a first channel region that separates light-receiving pixels by forming a potential barrier within the channel regions. a transfer electrode, a second transfer electrode that stores the photocharge by forming a potential well between the potential barrier formed in the first transfer electrode, and a second transfer electrode that is divided along the first transfer electrode. a color separation filter in which each region is associated with each light-receiving pixel, and each divided region transmits incident light of a specific wavelength; In the second period, a potential well is formed in the channel region by the first transfer electrodes in even-numbered columns to combine the photocharges of adjacent light-receiving pixels, and in the odd-numbered field, a potential well is formed in the channel region. During the period, potential wells are formed in the channel region by the second transfer electrodes in odd-numbered columns to combine the photocharges of adjacent light-receiving pixels, and during the following third period, the second transfer electrodes in the odd-numbered columns form a potential well in the channel region. The photoelectric charge is transferred along the channel region by pulse driving.

(Main) Effect According to the present invention, the potentials of the first and second transfer electrodes during the period of accumulating photocharges are the same in even and odd fields, and the photocharges accumulated in both fields are the same. becomes. Then, at the end of the photocharge accumulation period, the potential barrier between the pixels to be mixed is eliminated and the photocharges of the two pixels are mixed, and then the transfer electrodes are pulse-driven with a multiphase transfer clock. By transferring, a color component signal with a good balance between even and odd fields is output.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a timing diagram showing the method for driving a solid-state image sensor according to the present invention, and FIG. 2 is a diagram showing the state of the potentiometer at each timing. In this figure, the XY cross section of FIG. 3 is shown similarly to FIG. 5.

In the even field EVEN, during the photocharge accumulation period, the transfer clock φ1φ is fixed at a high potential, and the transfer clocks φ, φ4 are fixed at a low potential, and the transfer clocks φ, φ4 are formed as shown in T in FIG. Each pixel is separated by a potential barrier, and color components (W, Ye,
Cy) photocharges are accumulated.

This solid-state image sensor uses a vertical over-drain method that discharges excess photocharge to the substrate side.
By controlling the potential on the substrate side, the portion of the potential barrier formed by the transfer clocks φ and φ4 is configured to become an insensitive region, and mixing of photocharges is prevented. That is,
In a vertical overbroad drain type solid-state imaging device, depending on the potential of the transfer electrode and the potential on the substrate side, all the photocharges generated in the channel region are discharged to the substrate side, so the transfer clocks φ1 to φ, If the potential on the substrate side is set so that the photocharge flows from the channel region to the substrate side when is at a low potential, there will be no effective light receiving sensitivity when the transfer clocks φ1 to φ4 are at a low potential.

Then, at the end of the photocharge accumulation period, the transfer clock φ
, is set to a high potential, and the photocharges of two pixels are mixed as shown at T in FIG. The photocharges in the potential well that had been formed are transferred using clocks φ and φ.
, transfer to the potential well formed by . In the subsequent transfer period, the mixed photocharges of two pixels are transferred by four-phase driving of the transfer clocks φ□ to φ4.

Also, in the odd field ODD, the transfer clocks φ, φ are at a high potential during the photocharge accumulation period, and the transfer clocks φ, φ4 are at a high potential.
is fixed at a low potential, a potential barrier and a well as shown at T1 in FIG. 2 are formed as in the even field EVEN, and photocharges of color components corresponding to each pixel are accumulated.

Then, at the end of the photocharge accumulation period, the transfer clock φ
4 is set to a high potential, and the photocharges of the two pixels are mixed as shown at T4 in FIG. After this, the transfer clock φ is set to a low potential, and the photocharges in the potential well formed by the transfer clock φ are transferred to the potential well formed by the transfer clock φ4φ, and in the subsequent transfer period, the even field E
Similar to VEN, the data is transferred using four-phase drive of transfer clocks φ and φ.

Therefore, even field EVEN and odd field OD
D and color component signals W+Ya, W+Cy, Cy+ respectively.
G and Ye+G are obtained, and a luminance signal and a color signal are created by calculating these color component signals. The calculation of this color component signal is the same as the conventional one, and the explanation will be omitted.

In the interlaced drive as described above, the potential of the transfer electrode during the photocharge transfer period is equal in the even field EVEN and the odd field ODD, and the photocharge accumulation in both fields is performed at the same voltage. Therefore, there is no difference in the video signals between the two fields. Also,
The photocharges accumulated in each pixel are transferred sequentially after the two pixels are mixed with the transfer clock φ or φ4 at a high potential. Unnecessary mixing of components can be prevented.

(g) Effects of the Invention According to the present invention, a frame transfer type solid-state image sensor equipped with a mosaic filter can be driven in interlace mode without flickering.
By employing the driving method of the present invention, a television camera with high horizontal resolution can be provided.

[Brief explanation of drawings]

Fig. 1 is a timing diagram showing the driving method of the solid-state image sensor of the present invention, Fig. 2 is a diagram showing the potential state at the timing of Fig. 1, and Fig. 3 shows the light-receiving surface of the solid-state image sensor of the frame transfer method. FIG. 4 is a plan view, a timing diagram showing a conventional method for driving a solid-state image sensor, and FIG. 5 is a diagram showing potential states at each timing in FIG. (1)...channel region, (2)...channel separation region, (3)(4)...transfer electrode, (10)...
...Color separation filter.

Claims (3)

[Claims] (1) A plurality of channel regions, which are divided by separation regions and arranged parallel to each other, where photocharges generated by photoelectric conversion are accumulated and transferred, and a potential barrier is formed within these channel regions to separate light-receiving pixels. a first transfer electrode that stores the photocharge by forming a potential well between a potential barrier formed in the first transfer electrode; a color separation filter in which each area divided along the axis corresponds to each light-receiving pixel, and each divided area transmits incident light of a specific wavelength; , in the even field, a potential well is formed in the channel region by the first transfer electrodes in the even columns in the second period to combine the photocharges of adjacent light receiving pixels, and in the odd field, In the second period, a potential well is formed in the channel region by the second transfer electrodes in odd-numbered columns to combine the photocharges of adjacent light receiving pixels, and in the subsequent third period, the first and second transfer electrodes are combined. A method for driving a solid-state imaging device, comprising transferring the photocharge along the channel region by pulse-driving a transfer electrode. (2) The channel region is formed in a diffusion region of an opposite conductivity type buried in one surface of a semiconductor substrate of one conductivity type, and excess photocharge in the channel region is discharged to the semiconductor substrate side. A method for driving a solid-state image sensor according to claim 1. (3) The solid state according to claim 1, wherein the first and second transfer electrodes have a multilayer structure insulated from each other, and each transfer electrode is supplied with a four-phase transfer clock. How to drive the image sensor.