JP2009159634A - Solid-state imaging apparatus, driving method thereof and camera system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent signal charge from overflowing in a vertical transfer section and a horizontal transfer section with addition of the signal charge, without increasing a frequency of a vertical transfer clock, when adding the signal charge in the vertical transfer section and in the horizontal transfer section while performing a line thinning-out operation. <P>SOLUTION: When an addition reading mode is set, signal charge read from a sensor section 11 through a line thinning-out operation is added and vertically transferred for (n) pixels within a vertical transfer section 13, and added and horizontally transferred for (m) lines within a horizontal transfer section 15 thereafter. A substrate bias Vsub2 of a voltage value corresponding to a saturation signal charge amount of the sensor section 11 during the addition reading mode is generated by a substrate bias generating circuit 20 so that the saturation signal charge amount is set to be about 1/(n×m) during a frame reading mode, and this substrate bias is applied to a semiconductor substrate 18. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a solid-state imaging device, a driving method thereof, and a camera system, and more particularly to a solid-state imaging device configured to add signal charges in a charge transfer unit, a driving method thereof, and a camera system using the solid-state imaging device as an imaging device. .

  In recent years, solid-state imaging devices, particularly digital still cameras using a CCD (Charge Coupled Device) imaging device as an imaging device are rapidly spreading. In this digital camera, in order to give priority to resolution when shooting a still image, so-called all-pixel readout method in which signal charges of all pixels are read simultaneously at the same time and signal charges of each pixel are transferred independently, or A so-called frame readout type CCD image pickup device is used that alternately reads out signal charges of pixels on odd lines and even lines for each field and independently transfers signal charges of each pixel.

  FIG. 24 is a conceptual diagram of this frame reading operation. Here, as an example, a case where a color filter of a primary color 2 × 2 array is used is shown as an example. FIG. 25 shows the vertical synchronization timing of the four-phase vertical transfer clocks φV1 to φV4, and FIG. 26 shows the horizontal synchronization timing.

  On the other hand, when processing such as auto focus (AF) control, auto white balance (AWB) control, automatic exposure (AE) control, etc. is performed, the same operation mode as that for a still image is used. This is not preferable in terms of the response speed, and in particular, when a CCD image pickup device with a high pixel count is used, there is a problem that the response speed becomes slower. Also, when monitoring a captured image on a liquid crystal monitor or the like, using the same operation mode as that for a still image is not preferable because a smooth moving image cannot be obtained because the frame rate is low.

  One method for increasing the frame rate is to increase the data rate of the output signal of the CCD image sensor. However, in order to increase the data rate of the output signal, it is necessary to provide a sampling rate converter, and as the clock frequency increases, the power consumption increases and the cost of components used increases. Furthermore, new problems such as deterioration of S / N arise. Therefore, it is not preferable to employ a method for increasing the data rate of the output signal of the CCD image sensor.

  On the other hand, a read pulse is applied to a read gate unit for reading signal charges from the pixels for each predetermined repeating unit, and only the signal charges of the pixels of some lines are read to the vertical transfer unit, thereby outputting There is a so-called line thinning operation in which the number of lines to be processed is reduced to obtain a higher-speed imaging signal (that is, the frame rate is increased).

  FIG. 27 is a conceptual diagram of this line thinning operation. Here, as an example, a case where a signal charge of only 2 pixels out of 8 vertical pixels is read using a color filter of a primary color 2 × 2 array is shown as an example. FIG. 28 shows the vertical synchronization timing of the four-phase vertical transfer clocks φV1 to φV4, and FIG. 29 shows the horizontal synchronization timing. In the line thinning operation, two systems of φV1A / φV1B and φV3A / φV3B are generated for the first-phase and third-phase vertical transfer clocks φV1 and φV3.

  In this line thinning operation, 8 pixels are used as a repeating unit in the row direction (vertical direction), signal charges of only 2 pixels of these 8 pixels are read, and vertical transfer for 2 lines is performed within the horizontal blanking period. A packet in which signal charge exists and an empty packet are added. As a result, the number of output lines is reduced to 1/4 with respect to the previous frame reading operation, but the frame rate can be improved four times. At this time, the signal charges for two lines are added in the horizontal transfer unit, but since the packet in which the signal charges exist and the empty packet are added, the saturation signal charge amount of the sensor unit is equivalent to that in the frame reading operation. .

  According to this line thinning operation, it is possible to obtain a higher-speed imaging signal without increasing the data rate. However, when this line thinning operation is used, the number of output lines is thinned, so that the image quality deteriorates, or it is necessary to increase the number of lines to be thinned in a CCD image sensor having a larger number of pixels, and the image quality further deteriorates. There is a problem of end up.

  As another method for increasing the frame rate when performing various automatic control processes such as AF, AWB, and AE, or when monitoring with a liquid crystal monitor or the like, vertical transfer is used instead of thinning out lines. There are also methods in which signal charges are added between pixels (hereinafter referred to as pixel addition) in a unit, or signal charges are added between lines (hereinafter referred to as line addition) in a horizontal transfer unit.

  According to this method, since the number of output lines is reduced by performing pixel addition or line addition, the image quality can be improved as compared with the case where signal charges of lines that are not output are discarded as in the line thinning-out operation. In addition, there is a merit that sensitivity can be improved.

  On the other hand, the amount of charge in the vertical transfer unit or horizontal transfer unit increases to the number of pixels to be added (mixed) or the number of lines to be multiplied. There is a problem that signal charges overflow in the transfer section. In order to solve this problem, it is conceivable to design the vertical transfer unit or horizontal transfer unit so that charges equivalent to the number of pixels to be added or the number of lines can be handled. Therefore, the drive voltage must be increased, resulting in an increase in power consumption.

  In addition, in the conventional design of the vertical transfer unit or the horizontal transfer unit, the saturation signal charge amount of the sensor unit (pixel) is determined by the pixel addition mode, so that each pixel addition or line addition is not performed. The saturation signal charge amount of the sensor unit in the mode in which the signal charges of the pixels are transferred independently is approximately 1 / X, where X is the number of pixels to be added. However, reducing the saturation signal charge amount of the sensor unit deteriorates characteristics such as S / N and dynamic range, so it is not preferable to perform in a mode for taking a still image with priority on image quality.

Based on the above, assuming that line addition is performed in the horizontal transfer unit, in the monitoring mode, by setting the saturation signal charge amount of the sensor unit to about half of the saturation signal charge amount in the still image mode, A solid-state imaging device has been proposed in which signal charges added in the horizontal transfer unit are prevented from overflowing as line addition is performed (see, for example, Patent Document 1 ).

JP-A-5-91417

  However, in the above-described conventional technique, in the monitoring mode, by setting the saturation signal charge amount of the sensor unit to about half, it is possible to prevent the signal charge from overflowing in the horizontal transfer unit due to the line addition. Since the addition is performed by transferring the signal charges for two lines from the vertical transfer unit to the horizontal transfer unit within the horizontal blanking period, the following problem occurs.

  That is, since the horizontal blanking period is a limited period, in order to perform line transfer of signal charges for two lines within the limited horizontal blanking period, it is necessary to double the transfer rate. There is. Increasing the transfer rate of line transfer is to increase the frequency of the vertical transfer clock that drives the vertical transfer unit by a factor of two. As a result, the frequency of the vertical transfer clock is increased. If the amount of charge handled in the vertical transfer unit is insufficient due to propagation delay or the like, and the pixel is saturated or close to it, the signal charge may overflow or problems such as unnecessary radiation may occur.

The present invention has been made in view of the above problems, and its object is to perform vertical transfer when signal charges are added (mixed) in a vertical transfer unit and a horizontal transfer unit while performing a line thinning operation. To provide a solid-state imaging device, a driving method thereof, and a camera system capable of preventing overflow of signal charges in a vertical transfer unit and a horizontal transfer unit due to addition of signal charges without increasing a clock frequency. It is in.

In order to achieve the above object, in the present invention, a plurality of sensor units arranged in a matrix and performing photoelectric conversion, a vertical transfer unit that vertically transfers signal charges read from these sensor units, and the vertical transfer A solid-state imaging device having a horizontal transfer unit that horizontally transfers the signal charge transferred from the unit, and as an operation mode of the solid-state imaging device, a signal charge read from a plurality of sensor units is independently vertically transferred. In the first operation mode, after the signal charges of only pixels of a predetermined repeating unit are read from the plurality of sensor units, the signal charges for the plurality of pixels are added and transferred in the vertical transfer unit and the horizontal transfer unit. In the second operation mode, the signal charges for n pixels (n ≧ 2) are added and vertically transferred in the vertical transfer unit, and then in the horizontal transfer unit. m line (m ≧ 2 By adding the amount of signal charges to the horizontal transfer. Then, the saturation signal charge amount of the sensor unit in the second operation mode is set to about 1 / (n × m) of the saturation signal charge amount of the sensor unit in the first operation mode .

In the above configuration, in the second operation mode, the signal charges of only pixels of a predetermined repeating unit are read out, the signal charges of other pixels are thinned out, and the read signal charges are added by n pixels in the vertical transfer unit and horizontally transferred. m by pixel addition in part, as compared with the case of the first operation mode in which the vertical transfer independently without adding, frame rate because it reduces the number of output lines can improve than the first operation mode. In addition, by setting the saturation signal charge amount of the sensor unit in the second operation mode to about 1 / (n × m) of the saturation signal charge amount in the first operation mode, the signal charge amount after addition is reduced. It becomes equal to the signal charge amount read in the first operation mode.

According to the present invention, when signal charges are added in the vertical transfer unit and the horizontal transfer unit while performing a line thinning operation, the saturation signal charge amount of the sensor unit in the second operation mode is set to the value in the first operation mode. By setting the saturation signal charge amount to about 1 / (n × m), the signal charge amount after addition in the second operation mode becomes equal to the signal charge amount read in the first operation mode. Therefore, it is possible to prevent the added signal charges from overflowing in the vertical transfer unit and the horizontal transfer unit.

1 is a schematic configuration diagram illustrating a solid-state imaging element according to a first embodiment of the present invention. It is a wave form diagram showing the relation between control voltage DCIN given to a substrate bias generation circuit, and substrate bias Vsub. It is sectional drawing which shows the structure of the substrate depth direction around a sensor part. It is a potential diagram in the substrate depth direction around the sensor unit. It is a schematic block diagram which shows the 1st specific example of 1st Embodiment. It is a vertical-synchronization timing chart in the case of a 1st specific example. It is a horizontal synchronization timing chart in the case of the 1st example. It is a schematic block diagram which shows the 2nd specific example of 1st Embodiment. It is a vertical synchronization timing chart in the case of the 2nd example. It is a horizontal synchronization timing chart in the case of the 2nd example. It is a schematic block diagram which shows the solid-state image sensor which concerns on 2nd Embodiment of this invention. It is a wiring pattern diagram of an example of a transmission system of a vertical transfer clock for realizing a line thinning operation. FIG. 4 is a waveform diagram of a read pulse XSG, where (A) shows a case of a frame read operation mode, and (B) shows a case of a line thinning operation mode. It is a schematic block diagram which shows the 1st specific example of 2nd Embodiment. It is a vertical-synchronization timing chart in the case of a 1st specific example. It is a horizontal synchronization timing chart in the case of the 1st example. It is a schematic block diagram which shows the 2nd specific example of 2nd Embodiment. It is a vertical synchronization timing chart in the case of the 2nd example. It is a horizontal synchronization timing chart in the case of the 2nd example. It is a schematic block diagram which shows the 3rd specific example of 2nd Embodiment. It is a vertical-synchronization timing chart in the case of a 3rd example. It is a horizontal synchronization timing chart in the case of the 3rd example. It is a block diagram which shows an example of a structure of the camera system which concerns on this invention. It is a conceptual diagram of a frame reading operation. It is a vertical synchronization timing chart in the case of a frame reading operation. It is a horizontal synchronization timing chart in the case of a frame read-out operation. It is a conceptual diagram of line thinning-out operation | movement. It is a vertical synchronization timing chart in the case of line thinning-out operation. It is a horizontal synchronization timing chart in the case of line thinning-out operation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a solid-state imaging device according to the first embodiment of the present invention. In this embodiment, the case where an interline transfer (IT) type CCD image sensor is used will be described as an example.

  In FIG. 1, a plurality of sensor units 11 that are arranged in a matrix and convert incident light into signal charges having a charge amount according to the amount of light and are provided for each vertical column of the sensor units 11. An imaging area 14 is configured by a plurality of vertical transfer units 13 formed of a CCD for vertically transferring signal charges read from the unit 11 by the read gate unit 12.

  In the imaging area 14, the sensor unit 11 is made of, for example, a PN junction photodiode. The signal charges accumulated in the sensor unit 11 are read out to the vertical transfer unit 13 when a read pulse described later is applied to the read gate unit 12. The vertical transfer unit 13 is driven to transfer by, for example, four-phase vertical transfer clocks φV1 to φV4, and the read signal charges are sequentially arranged in the vertical direction in portions corresponding to one scanning line (one line) within the horizontal blanking period. Forward.

  Here, in the vertical transfer unit 13, the first-phase and third-phase transfer electrodes also serve as the gate electrode of the read gate unit 12. Therefore, among the four-phase vertical transfer clocks φV1 to φV4, the first-phase transfer clock φV1 and the third-phase transfer clock φV3 are low level (hereinafter referred to as “L” level), intermediate level (hereinafter referred to as “L” level). The three values of “M” level and high level (hereinafter referred to as “H” level) are set, and the third “H” level pulse is read out by the read gate section 12. It becomes a pulse XSG.

  On the lower side of the image pickup area 14 in the drawing, a horizontal transfer unit 15 made of a CCD is disposed. Signal charges corresponding to one line are sequentially transferred from the plurality of vertical transfer units 13 to the horizontal transfer unit 15. The horizontal transfer unit 15 is driven to transfer by, for example, two-phase horizontal transfer clocks φH1 and φH2, and the signal charge for one line transferred from the plurality of vertical transfer units 13 is transferred in the horizontal scanning period after the horizontal blanking period. Transfer sequentially in the horizontal direction.

  At the end of the horizontal transfer unit 15 on the transfer destination side, for example, a charge voltage conversion unit 16 having a floating diffusion amplifier configuration is provided. The charge / voltage converter 16 sequentially converts the signal charges horizontally transferred by the horizontal transfer unit 15 into signal voltages and outputs them. This signal voltage is derived from the output terminal 17 as a CCD output VOUT corresponding to the amount of incident light from the subject.

  The sensor unit 11, the read gate unit 12, the vertical transfer unit 13, the horizontal transfer unit 15, the charge voltage conversion unit 16, and the like described above are formed on a semiconductor substrate (hereinafter simply referred to as a substrate) 18. Thus, the interline transfer type CCD image pickup device 10 is configured.

  The above-described vertical transfer clocks φV1 to φV4 and horizontal transfer clocks φH1 and φH2 for driving the CCD image pickup device 10 are generated by the timing generation circuit 19. This timing generation circuit 19 functions as a driving means for driving the CCD image pickup device 10 and is accumulated in each of the sensor units 11 at the time of the electronic shutter other than the vertical transfer clocks φV1 to φV4 and the horizontal transfer clocks φH1 and φH2. Various timing signals such as a shutter pulse φSUB to be applied to the substrate 18 in order to sweep signal charges to the substrate 18 at once are appropriately generated.

  A substrate bias generation circuit 20 that generates a bias voltage (hereinafter referred to as substrate bias) Vsub for biasing the substrate 18 is provided outside the substrate 18. The substrate bias Vsub generated by the substrate bias generation circuit 20 is applied to the substrate 18 via the terminal 21 after passing through the diode D. The amount of saturation signal charge of the sensor unit 11 of the CCD image pickup device 10 is determined by the voltage value of the substrate bias Vsub. The principle will be described later.

  On the other hand, the shutter pulse φSUB generated by the timing generation circuit 19 is DC cut by the capacitor C and then applied to the substrate 18 via the terminal 21. A resistor R is connected between the terminal 21 and the ground. The diode D functions to clamp the “L” level of the shutter pulse φSUB to the DC level of the substrate bias Vsub.

  In this example, the configuration in which the substrate bias generation circuit 20 is provided outside the substrate 18 is employed. However, the substrate bias generation circuit 20 may be formed on the substrate 18 together with the diode D.

  The substrate bias generation circuit 20 functions as saturation signal charge amount setting means for switching the saturation signal charge amount of the sensor unit 11 in, for example, two stages by changing the voltage value of the substrate bias Vsub according to the operation mode. That is, as an example, a frame readout mode in which signal charges are read every other line for each field, and an addition readout mode in which signal charges of n pixels (n ≧ 2) are added and vertically transferred in the vertical transfer unit 13. The substrate bias Vsub having a different voltage value is generated.

  Specifically, as shown in FIG. 2, the substrate bias generation circuit 20 generates the substrate bias Vsub1 and the control voltage DCIN becomes “H” level in the frame read mode in which the control voltage DCIN becomes “L” level. In the addition reading mode, a substrate bias Vsub2 having a voltage value higher than the substrate bias Vsub1 is generated. Here, the voltage value of the substrate bias Vsub1 in the frame reading mode is set to an optimum value for each substrate 18 in consideration of a variation in potential of an overflow barrier, which will be described later, in the sensor unit 11 due to variation in manufacture of each device.

  On the other hand, the voltage value of the substrate bias Vsub2 in the addition reading mode is equal to the saturation signal charge amount of the sensor unit 11 in the frame reading mode when the signal charges for n pixels are added in the vertical transfer unit 13. The saturation signal charge amount is set to about 1 / n. Thus, in the addition reading mode, the substrate bias generation circuit 20 generates the substrate bias Vsub2 having a voltage value higher than the substrate bias Vsub1 in the frame reading mode, so that the saturation signal charge amount of the sensor unit 11 is read out by frame reading. It becomes about 1 / n in the mode.

FIG. 3 is a cross-sectional view showing the structure in the substrate depth direction around the sensor unit 11. In FIG. 3, for example, a P-type well region 31 is formed on the surface of an N-type substrate 18. An N ⁺ type signal charge storage region 32 is formed on the surface of the well region 31, and a P ⁺ type hole storage region 33 is further formed thereon, so that a so-called HAD (hole storage diode) structure is formed. The sensor unit 11 is configured.

  The charge amount of the signal charge e accumulated in the sensor unit 11 is determined by the height of the potential barrier of the overflow barrier OFB formed of the P-type well region 31 as shown in the potential distribution diagram of FIG. . In other words, the overflow barrier OFB determines the saturation signal charge amount Qs accumulated in the sensor unit 11, and when the accumulated charge amount exceeds the saturation signal charge amount Qs, the excess charge is potential. It is swept out to the substrate 18 side over the barrier.

  Thus, the sensor unit 11 having a so-called vertical overflow drain structure is configured. In the vertical overflow drain structure, the substrate 18 becomes an overflow drain. In this sensor unit 11, the saturation signal charge amount Qs is determined by the S / N characteristics of the device, the charge amount handled by the vertical transfer unit 13, etc., but the potential of the overflow barrier OFB varies due to manufacturing variations.

  The potential of the overflow barrier OFB is determined by the voltage value of the substrate bias Vsub described above. In other words, the saturation signal charge amount Qs of the sensor unit 11 is set by the voltage value of the substrate bias Vsub. Therefore, as described above, in the addition reading operation mode, the voltage value of the substrate bias Vsub2 becomes higher than that in the frame reading operation mode, so that the potential of the overflow barrier OFB becomes deeper by that amount. The signal charge amount Qs is about 1 / n.

In the lateral direction of the sensor unit 11, an N ⁺ type signal charge transfer region 35 and a P ⁺ type channel stopper region 36 are formed via a P type region 34 constituting the readout gate unit 12. Under the signal charge transfer region 35, a P ⁺ -type impurity diffusion region 37 for preventing the smear component from being mixed is formed. Further, a transfer electrode 39 made of, for example, polycrystalline silicon is disposed above the signal charge transfer region 35 via a gate insulating film 38, whereby the vertical transfer unit 13 is configured. In the transfer electrode 39, the portion located above the P-type region 34 also serves as the gate electrode of the read gate unit 12.

  An Al (aluminum) light-shielding film 41 is formed above the vertical transfer unit 13 via an interlayer film 40 so as to cover the transfer electrode 39. The Al light shielding film 41 is selectively removed by etching in the sensor unit 11, and light L from the outside enters the sensor unit 11 through the opening 42 formed by the etching removal. A substrate bias Vsub (Vsub1 / Vsub2) that determines the saturation signal charge amount Qs of the sensor unit 11 is applied to the substrate 18 via a terminal 21.

  Next, operations in each operation mode in the solid-state imaging device according to the first embodiment having the above-described configuration will be described.

(First example)
In the solid-state imaging device according to the first specific example, as shown in FIG. 5, the complementary colors (for example, Mg (magenta), Cy (cyan), and G are used as the CCD imaging device 10 in FIG. Assume that a CCD image pickup device having a 2 × 4 color filter of (green) and Ye (yellow)) is used. For the sake of simplicity, the case of a pixel array of 2 columns and 9 rows is shown as an example.

  The CCD image sensor 10 reads out the signal charges of the pixels on the odd lines and the even lines alternately for each field and transfers the signal charges of each pixel independently, and reads from each pixel. Two operation modes of an addition reading mode in which the signal charge is vertically transferred by adding, for example, two pixels in the vertical transfer unit 13 are set by various timing signals generated by the timing generation circuit 19. ing.

  First, when the frame reading mode is set, the control voltage DCIN of “L” level (see FIG. 2) is applied to the substrate bias generation circuit 20 in FIG. Then, the substrate bias generation circuit 20 generates the substrate bias Vsub1 set to an optimum value for each substrate 18 in consideration of variation in the potential of the overflow barrier of the sensor unit 11. The substrate bias Vsub1 is applied to the substrate 18 via the terminal 21.

  As described above, in the state where the substrate 18 is biased by the substrate bias Vsub1, the frame reading operation is performed in order to realize the still image mode. That is, an operation is performed in which the signal charges of the pixels on the odd lines and the even lines are alternately read for each field, the signal charges of the pixels are independently vertically transferred, and further horizontally transferred. Since this frame readout operation is well known, detailed description of the operation is omitted here.

  Next, when the addition reading mode is set, the “H” level control voltage DCIN (see FIG. 2) is applied to the substrate bias generation circuit 20. Then, the substrate bias generation circuit 20 generates a substrate bias Vsub2 having a voltage value corresponding to the addition of two pixels in the vertical transfer unit 13. The substrate bias Vsub2 is applied to the substrate 18 via the terminal 21. In this way, by biasing the substrate 18 with the substrate bias Vsub2 having a voltage value corresponding to the two-pixel addition in the vertical transfer unit 13, the saturation signal charge amount of the sensor unit 11 in this addition reading mode is obtained by frame reading. It is set to about ½ of the saturation signal charge amount in the mode.

  Here, the operation in the addition reading mode will be described with reference to the timing charts of FIGS. 6 shows the vertical synchronization timing of the four-phase vertical transfer clocks φV1 to φV4, and FIG. 7 shows the horizontal synchronization timing.

  First, in the timing chart of FIG. 6, the “H” level read pulse XSG is set in the vertical transfer clocks φV1 and φV3 of the first phase and the third phase at a certain timing of the vertical blanking period. The signal charges are read out by the vertical transfer unit 13, and the signal charges are added between two pixels adjacent in the row direction in the vertical transfer unit 13. Specifically, as is clear from FIG. 5, for each pixel in the first row and each pixel in the second row, for each pixel in the third row and each pixel in the fourth row, For each pixel in the sixth row,... And so on, two-pixel addition of signal charges is performed in the vertical transfer unit 13.

  Then, the signal charges for two rows obtained by adding two pixels are used as signal charges for one line, and in the horizontal blanking period, the vertical transfer for one line is performed according to the timing relationship shown in FIG. 7 of the four-phase vertical transfer clocks φV1 to φV4. Transfer (line shift) is performed. As a result, signal charges are transferred line by line from the vertical transfer unit 13 to the horizontal transfer unit 15. Thereafter, the signal charges for one line are sequentially transferred horizontally by the horizontal transfer unit 15, converted into a signal voltage by the charge voltage conversion unit 16, and output as a CCD output VOUT.

  As described above, in the solid-state imaging device including the CCD imaging device 10 that can take two operation modes of the frame readout mode and the addition readout mode, the signal charge read from the sensor unit 11 is vertically transferred when the addition readout mode is set. For example, by adding two pixels in the unit 13 and then performing vertical transfer, the number of output lines is halved compared to the case of independently performing vertical transfer without adding signal charges. Is twice as large as the frame readout mode, and information of all pixels can be output, so that image quality and sensitivity can be improved.

  In addition, when the addition readout mode is set, the saturation signal charge amount of the sensor unit 11 is set to about ½ of the saturation signal charge amount in the frame readout mode, so that the signal read out in the frame readout mode is set. Since each charge amount of the charge and the signal charge for two pixels added in the vertical transfer unit 13 becomes equal, even if the sensor unit 11 is saturated or close to it, the vertical transfer unit is added along with the addition of two pixels. It is possible to prevent the signal charges from overflowing in the horizontal transfer unit 13 and the horizontal transfer unit 15.

  Further, the CCD image pickup device 10 has a structure in which no change is made and only the substrate bias Vsub applied to the substrate 18 is switched according to the operation mode. Therefore, the same image quality as that of the conventional image can be obtained when taking a still image by the frame reading operation.

  In the first specific example, two pixels are added in the vertical transfer unit 13 in the addition readout mode. However, the present invention is not limited to the addition of two pixels, and signal charges of three or more pixels are transferred vertically. It is also possible to add in the part 13. In this case, when the number of pixels to be added is n (n ≧ 2), the saturation signal charge amount of the sensor unit 11 determined by the substrate bias Vsub2 generated by the substrate bias generation circuit 20 is used as the saturation signal in the frame readout mode. By setting the charge amount to about 1 / n, it is possible to prevent overflow of signal charges in the vertical transfer unit 13 and the horizontal transfer unit 15 due to pixel addition.

  In the first specific example, the signal charge is added only in the vertical transfer unit 13. However, in addition to the pixel addition in the vertical transfer unit 13, line addition in the horizontal transfer unit 15 is performed. It is also possible to do so. As an example, an addition reading operation in the case of 2-pixel addition in the vertical transfer unit 13 + 2-line addition in the horizontal transfer unit 15 will be described below as a second specific example.

(Second specific example)
In the solid-state imaging device according to the second specific example, as shown in FIG. 8, a CCD imaging device having a 2 × 8 array of complementary color filters is used as the CCD imaging device 10 in FIG. 1 so that color separation is possible. Shall be used. For the sake of simplicity, the case of a pixel array of 3 columns and 9 rows is shown as an example.

  First, when the addition reading mode is set, an “H” level control voltage DCIN (see FIG. 2) is applied to the substrate bias generation circuit 20. Then, the substrate bias generation circuit 20 generates a substrate bias Vsub2 having a voltage value corresponding to the number of pixels to be added. In this example, the signal charges for 2 pixels in the vertical transfer unit 13 and 2 lines (= 2 pixels) are added in the horizontal transfer unit 15, so that the signal charges for 4 (= 2 × 2) pixels are added. Is set to the voltage value of the substrate bias Vsub2.

  In this way, the substrate 18 is biased by the substrate bias Vsub2 having a voltage value corresponding to the addition of the signal charges for a total of four pixels in the vertical transfer unit 13 and the horizontal transfer unit 15, thereby enabling the addition reading mode. The saturation signal charge amount of the sensor unit 11 is set to about ¼ of the saturation signal charge amount in the frame readout mode.

  Here, the operation in the addition readout mode in the case of the two-pixel addition in the vertical transfer unit 13 and the two-line addition in the horizontal transfer unit 15 will be described with reference to timing charts of FIGS. FIG. 9 shows the vertical synchronization timing of the four-phase vertical transfer clocks φV1 to φV4, and FIG. 10 shows the horizontal synchronization timing.

  First, in the timing chart of FIG. 9, the “H” level read pulse XSG is set in the vertical transfer clocks φV1 and φV3 of the first phase and the third phase at a certain timing of the vertical blanking period. The signal charges are read out by the vertical transfer unit 13, and the signal charges are added between two pixels adjacent in the row direction in the vertical transfer unit 13. Specifically, as is clear from FIG. 8, for each pixel in the first row and each pixel in the second row, for each pixel in the third row and each pixel in the fourth row, For each pixel in the sixth row,... And so on, two-pixel addition of signal charges is performed in the vertical transfer unit 13.

  Then, the signal charges for two lines obtained by adding two pixels are used as signal charges for one line, and signals for two lines are obtained by the timing relationship shown in FIG. 10 of the four-phase vertical transfer clocks φV1 to φV4 in the horizontal blanking period. Vertical transfer is performed on the charge. As a result, signal charges for two lines are continuously transferred from the vertical transfer unit 13 to the horizontal transfer unit 15.

  When the signal charges for two lines are transferred from the vertical transfer unit 13 to the horizontal transfer unit 15, as is apparent from the timing chart of FIG. By outputting the horizontal transfer clocks φH1 and φH2 for one phase, the horizontal transfer unit 15 performs horizontal transfer for one packet (hereinafter referred to as 1-bit shift). After this 1-bit shift, the signal charges for the subsequent one line are transferred from the vertical transfer unit 13 to the horizontal transfer unit 15.

  As described above, when transferring the signal charge from the vertical transfer unit 13 to the horizontal transfer unit 15, the horizontal transfer unit 15 first performs a 1-bit shift immediately after transferring the signal charge for one line, and then the next one line. As is apparent from FIG. 8, the signal charges in the upper and lower two lines, that is, the signal charges of the same color, are added in the horizontal transfer unit 15 by transferring the signal charges of the minute. Thereafter, the added signal charges are sequentially transferred horizontally by the horizontal transfer unit 15, converted to a signal voltage by the charge voltage conversion unit 16, and output as a CCD output VOUT.

  As described above, in the solid-state imaging device including the CCD imaging device 10 that can take two operation modes of the frame readout mode and the addition readout mode, for example, signal charges for two pixels in the vertical transfer unit 13 in the addition readout mode. After that, for example, signal charges for two lines are added in the horizontal transfer unit 15, so that the number of output lines is reduced to ¼ as compared with the case of transferring independently without adding signal charges. Therefore, the frame rate is four times that of the frame readout mode, and information on all pixels can be output, so that the image quality and sensitivity can be improved.

  In addition, when the addition readout mode is set, the saturation signal charge amount of the sensor unit 11 is set to, for example, about ¼ of the saturation signal charge amount in the frame readout mode, so that the readout is performed in the frame readout mode. Since the signal charges and the signal charges of the four pixels added in the vertical transfer unit 13 and the horizontal transfer unit 15 are equal to each other, even if the sensor unit 11 is at or near saturation, the vertical charge 2 It is possible to prevent the signal charges from overflowing in the vertical transfer unit 13 and the horizontal transfer unit 15 due to pixel addition + horizontal 2-line addition.

  Here, in order to perform the two-line addition in the horizontal transfer unit 15, the frequency of the four-phase vertical transfer clocks φV1 to φV4 is set as is apparent from the comparison of the timing charts of FIGS. It is necessary to set to 2 times. However, when combined with pixel addition in the vertical transfer unit 13, the frequency of the vertical transfer clocks φV1 to φV4 can be halved as compared with the case where the frame rate is increased only by line addition in the horizontal transfer unit 15.

  That is, for example, when the frame rate is increased by a factor of four, for example, when the frame rate is increased only by line addition in the horizontal transfer unit 15, a signal for four lines within a limited horizontal blanking period. Since charges are added, it is necessary to increase the frequency of the vertical transfer clocks φV1 to φV4 by four times. However, pixel addition in the vertical transfer unit 13 and line addition in the horizontal transfer unit 15 are performed. By combining them, it is possible to cope with this by simply doubling the frequency of the vertical transfer clocks φV1 to φV4.

  In the second specific example, two pixels are added in the vertical transfer unit 13 and two lines are added in the horizontal transfer unit 15 in the addition reading mode. However, the addition is limited to two pixels + two lines. It is also possible to add signal charges of 3 pixels or more + 3 lines or more. In this case, when the number of pixels to be vertically added is n (n ≧ 2) and the number of lines to be horizontally added is m (n ≧ 2), the sensor unit 11 is determined by the substrate bias Vsub2 generated by the substrate bias generation circuit 20. Is set to approximately 1 / (n × m) of the saturation signal charge amount in the frame readout mode, so that the signal charges in the vertical transfer unit 19 and the horizontal transfer unit 15 accompanying the pixel addition are set. Overflow can be prevented.

  FIG. 11 is a schematic configuration diagram showing a solid-state imaging device according to the second embodiment of the present invention. In the present embodiment, a case where an IT type CCD image sensor is used will be described as an example.

  In FIG. 11, a plurality of sensor units 51 that are arranged in a matrix and convert incident light into signal charges having a charge amount corresponding to the amount of light, and are provided for each vertical column of the sensor units 51. An imaging area 54 is configured by a plurality of vertical transfer units 53 each including a CCD that vertically transfers the signal charges read from the unit 51 by the read gate unit 52.

  In the imaging area 54, the sensor unit 51 is composed of, for example, a PN junction photodiode. The signal charges accumulated in the sensor unit 51 are read out to the vertical transfer unit 53 when a read pulse XSG is applied to the read gate unit 52. The vertical transfer unit 53 is driven to transfer by, for example, four-phase vertical transfer clocks φV1 to φV4, and sequentially reads the read signal charges in the horizontal direction in portions corresponding to one scanning line (one line) in the horizontal blanking period. Forward.

  Here, in the vertical transfer unit 53, the transfer electrodes of the first phase and the third phase also serve as the gate electrode of the read gate unit 52 as in the case of the first embodiment. Of the clocks φV1 to φV4, the first-phase transfer clock φV1 and the third-phase transfer clock φV3 are set to take three values of “L” level, “M” level, and “H” level. The third “H” level pulse becomes the read pulse XSG of the read gate unit 52.

  On the lower side of the image pickup area 54 in the drawing, a horizontal transfer unit 55 made of a CCD is disposed. Signal charges corresponding to one line are sequentially transferred from the plurality of vertical transfer units 53 to the horizontal transfer unit 55. The horizontal transfer unit 55 is driven to transfer by, for example, two-phase horizontal transfer clocks φH1 and φH2, and the signal charge for one line transferred from the plurality of vertical transfer units 53 is transferred in the horizontal scanning period after the horizontal blanking period. Transfer sequentially in the horizontal direction.

  At the end of the horizontal transfer unit 55 on the transfer destination side, for example, a charge voltage conversion unit 56 having a floating diffusion amplifier configuration is provided. The charge-voltage converter 56 sequentially converts the signal charges transferred horizontally by the horizontal transfer unit 55 into signal voltages and outputs the signal voltages. This signal voltage is derived from the output terminal 57 as a CCD output VOUT corresponding to the amount of incident light from the subject.

  The sensor unit 51, the read gate unit 52, the vertical transfer unit 53, the horizontal transfer unit 55, the charge voltage conversion unit 56, and the like described above are formed on the substrate 58. Thus, the interline transfer type CCD image pickup device 50 is configured.

  The above-described vertical transfer clocks φV1 to φV4 and horizontal transfer clocks φH1 and φH2 for driving the CCD image pickup device 50 are generated by a timing generation circuit 59. The timing generation circuit 59 functions as a driving unit that drives the CCD image sensor 50. Here, of the vertical transfer clocks φV1 to φV4, the vertical transfer clocks φV1 / φV3 of the first phase and the third phase are, for example, two vertical transfer clocks φV1A and φV1B / φV3A and φV3B are generated.

  FIG. 12 shows an example of a wiring pattern of transfer electrodes of the vertical transfer unit 53 for realizing thinning readout. Here, in the row direction (vertical direction), with 4 pixels as a repetitive unit, signal charges are read for the first two pixels, and signal charges are not read for the second two pixels, that is, two lines are thinned out every two lines. The case of thinning readout is shown as an example.

  In FIG. 12, a total of six bus lines 62-1 to 62-6 are wired to transmit vertical transfer clocks φV1A, φV1B, φV2, φV3A, φV3B, and φV4. The first-phase transfer electrode 63-1 is connected to the bus line 62-1 for transmitting the vertical transfer clock φV1A every three pixels, and the bus line 62-2 for transmitting the vertical transfer clock φV1B is connected to the bus line 62-2. The first-phase transfer electrodes 24-1 other than those connected to -1 are connected every three pixels, and the fourth-phase transfer electrode 63-4 is 1 on the bus line 62-3 for transmitting the vertical transfer clock φV2. Connected every other pixel.

  Further, a third-phase transfer electrode 63-3 is connected to the bus line 62-4 that transmits the vertical transfer clock φV3A every three pixels, and the bus line 62-5 that transmits the vertical transfer clock φV3B is connected to the bus line 62-4. The third-phase transfer electrode 63-3 other than the one connected to the second-phase transfer electrode 6-3 is connected every third pixel. Connected every other pixel.

  As described above, the vertical transfer clocks φV1A / φV1B and φV3A / φV3B are the read pulse XSG that drives the read gate unit 52 when the third “H” level pulse reads the signal charge from the sensor unit 51. Become. In the frame read operation, as shown in FIG. 13A, the read pulse XSG is generated in each of the vertical transfer clocks φV1A / φV1B and φV3A / φV3B, whereas in the line thinning operation, As shown in FIG. 13B, the read pulse XSG is set only in the vertical transfer clocks φV1A and φV3A.

  Referring again to FIG. 1, the timing generation circuit 59 includes the vertical transfer clocks φV1 (A / B), φV2, φV3 (A / B), φV4 and the horizontal transfer clocks φH1, φH2, and the sensor unit 51 at the time of the electronic shutter. Various timing signals such as a shutter pulse φSUB applied to the substrate 58 in order to sweep out the signal charges accumulated in the substrate all at once to the substrate 58 are appropriately generated.

  A substrate bias generating circuit 60 for generating a substrate bias Vsub for biasing the substrate 58 is provided outside the substrate 58. The substrate bias Vsub generated by the substrate bias generation circuit 60 is applied to the substrate 58 via the terminal 61 after passing through the diode D. The saturation signal charge amount of the sensor unit 51 of the CCD image pickup device 50 is determined by the voltage value of the substrate bias Vsub. The principle is as described in the solid-state imaging device according to the first embodiment.

  On the other hand, the shutter pulse φSUB generated by the timing generation circuit 59 is DC cut by the capacitor C and then applied to the substrate 58 via the terminal 61. A resistor R is connected between the terminal 61 and the ground. The diode D functions to clamp the “L” level of the shutter pulse φSUB to the DC level of the substrate bias Vsub.

  In this example, the substrate bias generation circuit 60 is provided outside the substrate 58. However, the substrate bias generation circuit 60 is formed on the substrate 58 together with the diode D, as in the first embodiment. It is also possible to adopt a configuration.

  The substrate bias generation circuit 60 functions as saturation signal charge amount setting means for switching the saturation signal charge amount of the sensor unit 51 in, for example, two stages by changing the voltage value of the substrate bias Vsub according to the operation mode. That is, as an example, the substrate bias Vsub having different voltage values is generated in the frame reading mode and the special reading mode.

  Here, the special readout mode refers to a line thinning readout operation in which a readout pulse XSG is applied to the readout gate unit 52 for each predetermined repeating unit to read out only the signal charges of pixels of some lines, and vertical transfer. This is an operation mode based on a combination with an addition read operation in which signal charges of N pixels (N ≧ 2) are added to at least one of the unit 53 and the horizontal transfer unit 55.

  Specifically, the substrate bias generation circuit 60 generates the substrate bias Vsub1 in the frame read mode in which the control voltage DCIN is at the “L” level, and the substrate bias Vsub1 in the special read mode in which the control voltage DCIN is at the “H” level. A substrate bias Vsub2 having a higher voltage value is generated. Here, the voltage value of the substrate bias Vsub1 in the frame readout mode is set to an optimum value for each substrate 58 in consideration of a variation in potential of an overflow barrier (to be described later) in the sensor unit 51 due to manufacturing variation of each device.

  On the other hand, the voltage value of the substrate bias Vsub2 in the special read mode is obtained when the signal charges for N pixels (N ≧ 2) are added at least in one of the vertical transfer unit 53 and the horizontal transfer unit 55. The saturation signal charge amount of the sensor unit 51 is set to be approximately 1 / N of the saturation signal charge amount in the frame readout mode. Thus, in the special read mode, the substrate bias generation circuit 60 generates the substrate bias Vsub2 having a voltage value higher than the substrate bias Vsub1 in the frame read mode, so that the saturation signal charge amount of the sensor unit 61 is read out by the frame read. It becomes about 1 / N in the mode.

  Next, the operation in the special readout mode in the solid-state imaging device according to the second embodiment having the above configuration will be described.

(First example)
In the solid-state imaging device according to the first specific example, as shown in FIG. 14, a CCD imaging device having a 2 × 8 color filter array of complementary colors is used as the CCD imaging device 50 in FIG. Shall be used. In the special readout mode according to this specific example, in addition to the line thinning-out operation for reading out signal charges from the sensor unit 51 for only two of the four pixels in the row direction (vertical direction), for example, using four pixels as a repeating unit. In the vertical transfer unit 53, for example, an addition read operation for adding signal charges for two pixels is performed.

  First, when the special read mode is set, the “H” level control voltage DCIN is applied to the substrate bias generation circuit 60. Then, the substrate bias generation circuit 60 generates a substrate bias Vsub2 having a voltage value corresponding to the number of pixels to be added in the vertical transfer unit 53. In this specific example, since the signal charges for two pixels are added in the vertical transfer unit 53, the voltage value of the substrate bias Vsub2 is set correspondingly.

  In this way, the substrate 58 is biased with the substrate bias Vsub2 having a voltage value corresponding to the addition of signal charges for a total of two pixels in the vertical transfer unit 53, so that the saturation signal of the sensor unit 51 in this special read mode is obtained. The charge amount is set to about ½ of the saturation signal charge amount in the frame readout mode.

  Here, the operation in the special readout mode in the case of the line thinning + two-pixel addition in the vertical transfer unit 53 will be described with reference to timing charts of FIGS. 15 shows the vertical synchronization timing of the four-phase vertical transfer clocks φV1 (A / B), φV2, φV3 (A / B), and φV4, and FIG. 16 shows the horizontal synchronization timing. Further, in FIG. 14, the relationship between the two vertical transfer clocks φV1A / φV1B and φV3A / φV3B given to each pixel and each pixel is shown beside each pixel.

  First, in the timing chart of FIG. 15, the “H” level read pulse XSG is set in the vertical transfer clocks φV1A and φV3A of the first phase and the third phase at a certain timing of the vertical blanking period. The signal charge of the sensor unit 51 is read out to the vertical transfer unit 53 every two pixels every time. This is the line thinning operation in this specific example. Then, the read signal charges for every two pixels are added in the vertical transfer unit 53.

  Specifically, as is apparent from FIG. 14, for each pixel in the first row and each pixel in the second row, for each pixel in the fifth row and each pixel in the sixth row, For each pixel in the tenth row,... And so on, signal charges are read from the sensor unit 51 to the vertical transfer unit 53 in units of two pixels, and every two pixels read in the vertical transfer unit 53. Signal charges are added.

  Then, the signal charges for two rows added by two pixels are used as signal charges for one line, and in the horizontal blanking period, four-phase vertical transfer clocks φV1 (A / B), φV2, φV3 (A / B), Vertical transfer of two lines is performed according to the timing relationship of φV4 shown in FIG. At this time, since there is no signal charge for the subsequent one line due to the line thinning operation, the signal charge for one line is transferred to the horizontal transfer unit 55. The signal charges for one line are sequentially transferred horizontally by the horizontal transfer unit 55, converted into a signal voltage by the charge / voltage conversion unit 56, and output as a CCD output VOUT.

  As described above, in the solid-state imaging device including the CCD imaging device 50 that can take two operation modes of the frame readout mode and the special readout mode, when the special readout mode is set, every two pixels in the row direction every two pixels. The readout of signal charges from the sensor unit 51 is thinned out (line thinning out), and the readout signal charges are added every two pixels in the vertical transfer unit 53, so that the signal charges are not thinned out and added. Since the number of output lines is reduced to 1/4 compared to the case of independently performing vertical transfer, the frame rate is four times that of the frame reading mode.

  Moreover, when the special readout mode is set, the saturation signal charge amount of the sensor unit 51 is set to about ½ of the saturation signal charge amount in the frame readout mode, so that the signal read out in the frame readout mode is set. Each charge amount of the charge and the signal charge for two pixels added in the vertical transfer unit 53 is equal, so even if the sensor unit 51 is saturated or close to it, the vertical transfer unit is added along with the addition of two pixels. It is possible to prevent the signal charges from overflowing in 53 and the horizontal transfer section 55 in advance.

  In the addition read operation according to the first specific example, two pixels are added in the vertical transfer unit 53. However, the addition is not limited to the two pixel addition, and signal charges of three or more pixels are transferred to the vertical transfer unit 53. It is also possible to add within. In this case, when the number of pixels to be added is n (n ≧ 2), the saturation signal charge amount of the sensor unit 51 determined by the substrate bias Vsub2 generated by the substrate bias generation circuit 60 is used as the saturation signal in the frame readout mode. By setting the charge amount to approximately 1 / n, it is possible to prevent overflow of signal charges in the vertical transfer unit 53 and the horizontal transfer unit 55 due to pixel addition.

(Second specific example)
In the solid-state imaging device according to the second specific example, a CCD imaging device having a 2 × 2 color filter of primary colors (R, G, B) as shown in FIG. 17 is used as the CCD imaging device 50 of FIG. Shall. In the special readout mode according to this example, the signal charge is read from the sensor unit 51 only for four of the 16 pixels, for example, with 16 pixels as a repeating unit in the row direction, in other words, 12 pixels per 16 pixels. In addition to the line thinning-out operation for thinning out the signal charges, for example, an addition reading operation for adding signal charges for two lines in the horizontal transfer unit 55 is performed.

  In the special readout mode according to the second specific example, signal charges for two lines (two pixels) are added in the horizontal transfer unit 55, so the voltage value of the substrate bias Vsub2 corresponding to the number of added lines. Is set. Thereby, the saturation signal charge amount of the sensor unit 51 in the special readout mode is set to about ½ of the saturation signal charge amount in the frame readout mode.

  In order to realize a line thinning operation for thinning out 12 pixels per 16 pixels, among the vertical transfer clocks φV1 to φV4, three vertical transfer clocks are used for the first and third phase vertical transfer clocks φV1 and φV3. φV1A / φV1B / φV1C and φV3A / φV3B / φV3C are generated by the timing generation circuit 59.

  Here, the operation in the special read mode in the case of this line thinning + two line addition in the horizontal transfer unit 52 will be described with reference to timing charts of FIGS. FIG. 18 shows the vertical synchronization timing of the four-phase vertical transfer clocks φV1 (A / B / C), φV2, φV3 (A / B / C), and φV4, and FIG. 19 shows the horizontal synchronization timing.

  In FIG. 17, the relationship between the three vertical transfer clocks φV1A / φV1B / φV1C and φV3A / φV3B / φV3C given to each pixel is shown beside each pixel. Note that the vertical transfer clocks φV1 (A / B / C), φV2, φV3 (A / B / C), and φV4 transmission systems are patterned in accordance with the wiring principle shown in FIG. Shall.

  First, in the timing chart of FIG. 18, the “H” level read pulse XSG is set in the vertical transfer clocks φV1A and φV3A of the first phase and the third phase at a certain timing of the vertical blanking period, so that 16 pixels are arranged in the row direction. As a repeating unit, the signal charge of the sensor unit 51 is read out to the vertical transfer unit 53 only for four of the 16 pixels. In other words, signal charges of 12 pixels are thinned out for 16 pixels. This is the line thinning operation in this specific example.

  Specifically, as apparent from FIG. 17, the signal charges are read out only for the pixels in the first row, the third row, the tenth row, and the twelfth row using the first row to the 16th row as a repeating unit. Then, signal charges are thinned out for the remaining pixels in the second, fourth to ninth, eleventh, and thirteenth to sixteenth rows. The read signal charges are sequentially added in the vertical transfer unit 53 without being added in the vertical transfer unit 53 and supplied to the horizontal transfer unit 55.

  When signal charges are transferred from the vertical transfer unit 53 to the horizontal transfer unit 55, four-phase vertical transfer clocks φV1 (A / B / C), φV2, φV3 (A / B / C), vertical transfer is performed in units of 4 lines (4 rows) according to the timing relationship shown in FIG. 19 for φV4. As a result, since the signal charges exist only for the first and third lines in the first four lines, the signal charges for two lines (two pixels) are added in the horizontal transfer unit 55. become. Thereafter, the signals are sequentially transferred horizontally by the horizontal transfer unit 55, converted into a signal voltage by the charge-voltage conversion unit 56, and output as a CCD output VOUT.

  As described above, when the special readout mode is set, the readout of signal charges from the sensor unit 51 is thinned out (line thinning out) for 12 pixels out of the 16 pixels in the row direction with 16 pixels as a repeating unit. As for the signal charges, two lines are added in the horizontal transfer unit 55, so that the number of output lines is reduced to 1/8 (in comparison with the case of independent vertical transfer without thinning out and adding the signal charges. = 4/16 ÷ 2), the frame rate is 8 times that of the frame reading mode.

  Moreover, when the special readout mode is set, the saturation signal charge amount of the sensor unit 51 is set to about ½ of the saturation signal charge amount in the frame readout mode, so that the signal read out in the frame readout mode is set. Since each charge amount of the charge and the signal charge for two lines added in the horizontal transfer unit 55 becomes equal, even if the sensor unit 51 is saturated or close to it, the horizontal transfer unit is added along with the addition of two lines. It is possible to prevent the signal charge from overflowing in 55.

  In addition, in the addition read operation according to the second specific example, two lines are added in the horizontal transfer unit 55. However, the addition is not limited to the two line addition. For example, as in the second specific example, 16 lines are added. In the case where the signal charges for four lines are read out using as a repeating unit, the signal charges for the four lines read out can be added in the horizontal transfer unit 55. In this case, the saturation signal charge amount in the special readout mode may be set to about 1/4 of that in the frame readout mode.

  Further, it is not necessary to fix the number of addition lines in the horizontal transfer unit 55 to one. For this line addition mode, for example, the number of addition lines is x (x ≧ 2) and y (x> y). It is also possible to set two or more types of operation modes in this case and to select them appropriately. In this case, the substrate bias Vsub2 generated by the substrate bias generation circuit 60 is set to each operation so that the saturation signal charge amount in each operation mode is about 1 / x and about 1 / y in the frame reading mode. Switching may be performed according to the mode.

(Third example)
In the solid-state imaging device according to the third specific example, as shown in FIG. 20, a CCD imaging device having a 2 × 2 array of primary color filters is used as the CCD imaging device 50 in FIG. Shall be used. In the special readout mode according to this specific example, the signal charge is read out from the sensor unit 51 only for 8 pixels out of the 16 pixels, for example, in the row direction, for example, 16 pixels, in other words, 8 pixels per 16 pixels. In addition to the line thinning-out operation for thinning out the signal charges, an addition reading operation for adding signal charges for, for example, four lines in the horizontal transfer unit 55 is performed.

  In the special read mode according to the third specific example, signal charges for 4 lines (4 pixels) are added in the horizontal transfer unit 55, and therefore the voltage value of the substrate bias Vsub2 corresponding to the number of added lines. Is set. Thereby, the saturation signal charge amount of the sensor unit 51 in the special readout mode is set to about ¼ of the saturation signal charge amount in the frame readout mode.

  Further, in order to realize a line thinning operation for thinning out 8 pixels per 16 pixels, the vertical transfer clocks φV1 and φV3 of the first and third phases among the vertical transfer clocks φV1 to φV4 are the case of the second specific example. Similarly, the three vertical transfer clocks φV1A / φV1B / φV1C and φV3A / φV3B / φV3C are generated by the timing generation circuit 59.

  Here, the operation in the special read mode in the case of this line thinning + four lines addition in the horizontal transfer section 52 will be described with reference to the timing charts of FIGS. FIG. 21 shows the vertical synchronization timing of the four-phase vertical transfer clocks φV1 (A / B / C), φV2, φV3 (A / B / C), and φV4, and FIG. 22 shows the horizontal synchronization timing.

  In FIG. 20, the correspondence between the three vertical transfer clocks φV1A / φV1B / φV1C and φV3A / φV3B / φV3C given to each pixel is shown beside each pixel. Note that the vertical transfer clocks φV1 (A / B / C), φV2, φV3 (A / B / C), and φV4 transmission systems are patterned in accordance with the wiring principle shown in FIG. Shall.

  First, in the timing chart of FIG. 21, the “H” level read pulse XSG is set in the vertical transfer clocks φV1A / φV1B and φV3A / φV3B of the first phase and the third phase at a certain timing of the vertical blanking period. The signal charge of the sensor unit 51 is read out to the vertical transfer unit 53 for only 8 pixels out of the 16 pixels, with 16 pixels as a repeating unit in the direction. In other words, signal charges of 8 pixels are thinned out for 16 pixels. This is the line thinning operation in this specific example.

  Specifically, as is apparent from FIG. 20, the 1st to 16th lines are the units, the 1st, 3rd, 5th, 7th, 10th, 12th, and 14th lines. The signal charge is read for each pixel in the first and 16th rows, and the remaining 2nd, 4th, 6th, 8th, 9th, 11th, 13th and 15th rows The signal charge is thinned out for each pixel. The read signal charges are sequentially added in the vertical transfer unit 53 without being added in the vertical transfer unit 53 and supplied to the horizontal transfer unit 55.

  When signal charges are transferred from the vertical transfer unit 53 to the horizontal transfer unit 55, four-phase vertical transfer clocks φV1 (A / B / C), φV2, φV3 (A / B / C), vertical transfer is performed in units of 4 lines (4 rows) according to the timing relationship of φV4 shown in FIG. As a result, since the signal charges are present every other line for the first four lines, the signal charges for four lines (two pixels) are added in the horizontal transfer unit 55. Thereafter, the signals are sequentially transferred horizontally by the horizontal transfer unit 55, converted into a signal voltage by the charge-voltage conversion unit 56, and output as a CCD output VOUT.

  As described above, when the special readout mode is set, the readout of signal charges from the sensor unit 51 is thinned out (line thinning out) for 8 pixels out of 16 pixels in the row direction with 16 pixels as a repeating unit. With respect to signal charges, by adding four lines in the horizontal transfer section 55, the number of output lines is reduced to 1/8 (in comparison with the case of vertical transfer independently without thinning out and adding signal charges. = 8/16 ÷ 4), the frame rate is 8 times that of the frame reading mode.

  In addition, when the special readout mode is set, the saturation signal charge amount of the sensor unit 51 is set to about ¼ of the saturation signal charge amount in the frame readout mode, so that the signal read out in the frame readout mode is set. Since each charge amount of the charge and the signal charge for four lines added in the horizontal transfer unit 55 becomes equal, the horizontal transfer unit is added along with the addition of four lines even when the sensor unit 51 is saturated or close thereto. It is possible to prevent the signal charge from overflowing in 55.

  In the addition read operation according to the third specific example, 4-line addition is performed in the horizontal transfer unit 55. However, the addition is not limited to 4-line addition. For example, as in the third specific example, 16 lines are added. When signal charges for 8 lines are read out as a repeating unit, the read signal charges for 8 lines can be added in the horizontal transfer unit 55. In this case, the saturation signal charge amount in the special readout mode may be set to about 1/8 that in the frame readout mode.

  Further, it is not necessary to fix the number of addition lines in the horizontal transfer unit 55 to one. For this line addition mode, for example, the number of addition lines is x (x ≧ 2) and y (y> x). It is also possible to set two or more types of operation modes in this case and to select them appropriately. In this case, the substrate bias Vsub2 generated by the substrate bias generation circuit 60 is set to each operation so that the saturation signal charge amount in each operation mode is about 1 / x and about 1 / y in the frame reading mode. Switching may be performed according to the mode.

  In the first and second embodiments described above, a case in which the readout method for independently vertically transferring the signal charges read from each pixel is applied to a CCD image sensor of a frame readout method corresponding to interlace will be described as an example. However, the present invention is not limited to this, and the present invention can be similarly applied to a CCD image pickup device of an all-pixel readout method in which the signal charges of all the pixels are read simultaneously at the same time and the signal charges of each pixel are independently transferred. is there.

  Further, in each of the above embodiments, the saturation signal charge amount of each pixel at the time of pixel addition or line addition is calculated using the normal substrate bias Vsub in a CCD image pickup device having a vertical overflow drain structure (see FIG. 3). Although the configuration is set by changing the operation mode, it is not limited to this.

For example, in a CCD image sensor having a so-called horizontal overflow drain structure having an overflow drain for each pixel, pixel addition or line addition can be performed by changing the DC bias that determines the potential of the overflow barrier of each pixel according to the operation mode. The saturation signal charge amount of each pixel can be set.

  In addition, when the operation mode in which the addition is performed only in the horizontal transfer unit is adopted, an overflow drain beside the transfer channel for each vertical transfer unit in the VH transfer region for transferring signal charges from the vertical transfer unit to the horizontal transfer unit. It is also possible to set the saturation signal charge amount of each pixel at the time of line addition by changing the DC bias according to the operation mode by determining the overflow barrier potential by a DC bias. it can.

  FIG. 23 is a schematic configuration diagram of a camera system according to the present invention in which the solid-state imaging device according to each of the above embodiments is used as an imaging device. This camera system is used as a digital still camera, for example.

  In this camera system, as the CCD image sensor 71, the CCD image sensor according to the first embodiment described above, that is, a combination of frame readout (or all pixel readout) and vertical transfer unit pixel addition or horizontal transfer unit line addition. Readable CCD image sensor, CCD image sensor according to the second embodiment, ie, frame readout (or all pixel readout), readout by combination of thinning readout and vertical transfer unit pixel addition or horizontal transfer unit line addition A CCD image sensor capable of satisfying the above is used.

  On the image pickup surface of the CCD image pickup device 71, image light incident from a subject (not shown) is imaged through an optical system such as a lens 72. The CCD image pickup device 71 is driven by a CCD drive circuit 73 including the timing generation circuit 11/59 described above. A substrate bias Vsub generated by the substrate bias generation circuit 74 is applied to the substrate of the CCD image sensor 71. As the substrate bias generation circuit 74, the substrate bias generation circuit 20 described in the first embodiment or the substrate bias generation circuit 60 described in the second embodiment is used.

  The output signal (CCD output VOUT) of the CCD image pickup device 71 is output to the outside as an image pickup signal after various signal processing such as automatic white balance (AWB) adjustment is performed in the signal processing circuit 75 in the next stage. . In addition, an operation mode setting unit 76 for setting the operation mode of the CCD image sensor 71 is provided. In the operation mode setting unit 76, for example, a normal imaging mode for capturing a still image and a monitoring mode for monitoring a captured image with a liquid crystal monitor or the like are set.

  Mode information representing the operation mode set by the operation mode setting unit 76 is supplied to the CCD drive circuit 73, the substrate bias generation circuit 74, and the signal processing circuit 75. The CCD drive circuit 73 drives the CCD image sensor 71 so as to perform a frame readout operation (or all-pixel readout operation) when the normal imaging mode is set, and at the time of setting the monitoring mode, The CCD image sensor 71 is driven to perform the addition reading operation described in the second specific example or the special reading operations described in the first to third specific examples in the second embodiment.

  When the normal imaging mode is set, the substrate bias generation circuit 74 takes the CCD image of the substrate bias Vsub1 set to the optimum value in consideration of the variation in the potential of the overflow barrier of the sensor unit accompanying the variation in manufacturing of the CCD image sensor 71. When applied to the substrate of the element 71 and setting the monitoring mode, the saturation signal charge amount of the pixel is in the normal imaging mode when the number of added pixels is n (n ≧ 2) and the number of added lines is m (m ≧ 2). A substrate bias Vsub2 having a voltage value set to about 1 / n, about 1 / m, or about 1 / (n × m) is applied.

  As described above, in the camera system including the CCD image sensor 71, in the monitoring mode, the addition readout operation according to the first embodiment or the special readout operation according to the second embodiment is performed, and the saturation signal charge amount of the pixel Is set to about ½ of that in the normal imaging mode, for example, to prevent overflow of signal charges in the vertical transfer unit and horizontal transfer unit due to pixel addition or line addition, and the frame rate compared to that in the normal imaging mode. Therefore, the captured image can be monitored as a smooth video.

For the sake of simplification of explanation, the addition readout operation of the first embodiment or the special readout operation of the second embodiment is performed when the captured image is monitored by a liquid crystal monitor or the like. These readout operations are also performed when performing AF control, AWB control, AE control, and the like. In this case, since the response speed of various automatic control devices can be increased, it is possible to cope with the increase in the number of pixels of the CCD image pickup device 71, so that a higher-performance camera system can be realized.

  DESCRIPTION OF SYMBOLS 10, 50 ... CCD image sensor, 11, 51 sensor part, 13, 53 ... Vertical transfer part, 15, 55 ... Horizontal transfer part, 16, 56 ... Charge voltage conversion part, 19, 59 ... Timing generation circuit, 20, 60 ... Board bias generation circuit

Claims (9)

A plurality of sensor units arranged in a matrix to perform photoelectric conversion, a vertical transfer unit that vertically transfers signal charges read from these sensor units, and a horizontal transfer that horizontally transfers the signal charges transferred from the vertical transfer unit A solid-state imaging device having a transfer unit;
A first operation mode in which signal charges read from the plurality of sensor units are independently vertically transferred; and after reading signal charges of only pixels of a predetermined repeating unit from the sensor unit, in the vertical transfer unit and A second operation mode in which signal charges for a plurality of pixels are added and transferred in the horizontal transfer unit is selectively set , and in the second operation mode, n pixels (n Drive for driving the solid-state imaging device so that signal charges for ≧ 2) are added and vertically transferred, and then signal charges for m lines (m ≧ 2) are added and horizontally transferred in the horizontal transfer unit. Means,
Saturation signal charge amount setting for setting the saturation signal charge amount of the sensor unit in the second operation mode to about 1 / (n × m) of the saturation signal charge amount of the sensor unit in the first operation mode. And a solid-state imaging device. The substrate bias voltage for biasing the substrate on which the solid-state imaging device is formed is set such that a voltage value in the second operation mode is larger than a voltage value in the first operation mode. Solid-state imaging device. The solid-state imaging device according to claim 2, wherein the substrate bias voltage is applied via a diode to a terminal of the substrate connected to the ground via a resistor. The solid-state imaging device according to claim 1, wherein the second operation mode includes a line thinning readout operation for reading out signal charges of pixels of some lines. The solid-state imaging device according to claim 4, wherein the signal charges for n pixels are signal charges of two adjacent pixels. The vertical transfer unit is driven to transfer by a four-phase vertical transfer clock,
The signal charges of the two pixels are read from the sensor unit to the vertical transfer unit by the vertical transfer clock of the first phase and the vertical transfer clock of the third phase of the four-phase vertical transfer clocks, and the vertical transfer is performed. The solid-state imaging device according to claim 5, wherein the solid-state imaging device is added in a part. The solid-state imaging device according to claim 6, wherein the vertical transfer unit performs vertical transfer for two lines by the four-phase vertical transfer clock. A plurality of sensor units arranged in a matrix to perform photoelectric conversion, a vertical transfer unit that vertically transfers signal charges read from these sensor units, and a horizontal transfer that horizontally transfers the signal charges transferred from the vertical transfer unit in the driving of the solid-state imaging device including a solid-state imaging device having a transfer unit,
As a driving mode of the solid-state imaging device, a first operation mode in which signal charges read from the plurality of sensor units are independently vertically transferred, and signal charges of only pixels of a predetermined repeating unit are read from the sensor unit. And then selectively setting a second operation mode in which signal charges for a plurality of pixels are added and transferred in the vertical transfer unit and the horizontal transfer unit , and in the second operation mode , In the vertical transfer unit, signal charges for n pixels (n ≧ 2) are added and transferred vertically, and then in the horizontal transfer unit, signal charges for m lines (m ≧ 2) are added and transferred horizontally,
The saturation signal charge amount of the sensor unit in the second operation mode is set to about 1 / (n × m) of the saturation signal charge amount of the sensor unit in the first operation mode. Method. A plurality of sensor units arranged in a matrix to perform photoelectric conversion, a vertical transfer unit that vertically transfers signal charges read from these sensor units, and a horizontal transfer that horizontally transfers the signal charges transferred from the vertical transfer unit A solid-state imaging device having a transfer unit;
A first operation mode in which signal charges read from the plurality of sensor units are independently vertically transferred; and after reading signal charges of only pixels of a predetermined repeating unit from the sensor unit, in the vertical transfer unit and A second operation mode in which signal charges for a plurality of pixels are added and transferred in the horizontal transfer unit is selectively set , and in the second operation mode, n pixels (n Drive for driving the solid-state imaging device so that signal charges for ≧ 2) are added and vertically transferred, and then signal charges for m lines (m ≧ 2) are added and horizontally transferred in the horizontal transfer unit. Means,
Saturation signal charge amount setting for setting the saturation signal charge amount of the sensor unit in the second operation mode to about 1 / (n × m) of the saturation signal charge amount of the sensor unit in the first operation mode. And a camera system.

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