JPH09121310A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To individually adjust voltage to be impressed to a specific part of a semiconductor device without generating a large current by connecting a means for lowering the absolute value of potential to the input terminal of a clamp circuit. SOLUTION: The output voltage of a substrate bias circuit 25 is impressed to a semiconductor substrate through a diode 36 forming a clamp circuit. A control terminal 37 is connected so as to extract the input terminal of the anode side of the diode (clamp circuit) 36 to the external. A resistor 38 is connected between the terminal 37 and ground so as to drop the output voltage of the bias circuit 25, so that the output voltage of the diode 36 can be dropped correspondingly to the drop of the output voltage of the circuit 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, mainly a substrate bias voltage which is an output of a substrate bias circuit is applied to a substrate through a clamp circuit, and the substrate is electrically taken out to the outside. The present invention relates to a solid-state imaging device in which a signal such as a shutter pulse is applied to a substrate through a terminal.

[0002]

2. Description of the Related Art Many solid-state image pickup devices, such as CCD type solid-state image pickup devices, have an overflow drain structure. As a typical example, p is formed on the surface of an n-type semiconductor substrate.
Type semiconductor layer (well) is formed, a large number of n-type light receiving elements forming pixels on the surface of the p-type semiconductor layer, horizontal transfer CCD
Type register, vertical transfer CCD type register and the like are formed, the p-type semiconductor layer is grounded, and a positive substrate bias voltage Vsub is applied to the n-type semiconductor substrate.

The light receiving element, that is, the photoelectric conversion section is shown in FIG.
It has a potential profile in the depth direction as shown in. In the figure, a is an n-type light receiving element, which photoelectrically converts incident light. e is a charge accumulated in the light receiving element a. b is a potential barrier by a p-type semiconductor layer,
c is an n-type semiconductor substrate. Then, the potential barrier is changed by the voltage Vsub applied to the substrate, and the voltage Vsub
When is higher, the potential distribution moves deeper as shown by the broken line.

Therefore, the bias circuit which sets the value of the voltage Vsub to such a value that a potential distribution having a proper height of the potential barrier in a normal state is obtained and outputs a bias voltage having the value is used in the solid-state imaging. It is provided outside or inside the device. Further, the number of types of solid-state imaging devices that control the exposure time by controlling the charge accumulation time by each light-receiving element in the vertical cycle is increasing, and such solid-state imaging devices are configured by applying a high-level shutter pulse to the substrate. By appropriately performing the operation of forcibly discharging the signal charges in the light receiving element a to the substrate side, the charge accumulation time is substantially controlled. FIG. 8 shows an example of such a solid-state image pickup device, which is one of the solid-state image pickup devices proposed by the applicant company in Japanese Patent Application No. 6-98110.

In the figure, reference numeral 11a denotes a solid-state image pickup device, 1
Is a light receiving element arranged in a matrix in a column direction (vertical direction) and a row direction (horizontal direction), and 2 is a vertical transfer register provided corresponding to each vertical column of the light receiving element 1. The vertical transfer register 2 constitutes an imaging area 3. Reference numeral 4 denotes a horizontal transfer register, which inputs the signal charges transferred from each vertical transfer register 2 in parallel and transfers them in the horizontal direction. Reference numeral 5 denotes a charge detection unit having a floating diffusion structure, which is provided at the output end of the horizontal transfer register 5, 6 is an output amplifier, and 7 is a video signal output terminal.

Reference numeral 24 is a timing generator for generating each pulse φV1 to φV4, φH1, φH2 for controlling the solid-state image pickup device 11a and a shutter pulse SP, and 25 is a substrate bias generating circuit for generating the substrate bias voltage Vsub. The circuit configuration is as shown in (A) to (C). For another example of the bias circuit, Japanese Patent Application No. 6-154310 filed by the applicant of the present application has already been filed.
Have been introduced by. A diode 36 forms a clamp circuit, and the output voltage of the substrate bias circuit 25 is applied to the semiconductor substrate via the diode 36.

Reference numeral 33 is a terminal for drawing out the cathode side (the anode is connected to the substrate bias circuit 25) of the diode 36 to the outside, which serves as a shutter pulse input terminal, and the input terminal 33 has the above-mentioned timing generation. The shutter pulse SP from the circuit 24 is the capacitor 3
2 is input via Reference numeral 34 is a resistor connected between the shutter pulse input terminal 33 and the ground. According to such a solid-state imaging device, the substrate c can be biased so that an appropriate potential profile can be obtained by appropriately setting the output voltage of the bias circuit.

Then, when the shutter pulse SP is input, the diode 36 is in a reverse bias state, and the bias circuit 25 causes the diode 36 to cause the semiconductor substrate c.
Shutter pulse SP
Is transmitted to the semiconductor substrate c without any trouble. Therefore, the signals in all the light receiving elements a overflow the potential barrier in which the signals have become deep and are discharged to the substrate side. Therefore,
The bias profile 25 is the potential profile under normal conditions.
The control by the shutter pulse SP of the potential profile at the time of electronic shutter is performed without any trouble by blocking the involvement of the bias circuit 25 by the diode 36.

10A and 10B are circuit diagrams showing other examples of the clamp circuit. That is, the one shown in (A) uses a bipolar transistor instead of the diode, and the one shown in (B) replaces the diode with M.
It uses an OS transistor.

[0010]

The conventional solid-state image pickup device described above has a problem that the potential profile cannot be arbitrarily changed by the user. That is, some of the customers desire to be able to arbitrarily change the standard and performance set by the solid-state imaging device manufacturer. Specifically, some people want to be able to increase the dynamic range. And the reality is that we have not yet responded to that.

By the way, in order to increase the dynamic range, it is only necessary to forcibly reduce the voltage applied to the substrate during normal operation. Specifically, it means that a low voltage should be applied through the shutter pulse input terminal 33. However, according to the conventional solid-state imaging device as shown in FIG. 8, since the bias circuit 25 is provided inside, when a low voltage is forcibly applied to the substrate, the voltage is lower than the output voltage of the bias circuit 25. Therefore, the internal diode 36 (or bipolar transistor, M
The OS transistor) is turned on and a current is applied to the PN junction of the diode, and as a result, secondary electrons and secondary holes are generated. The secondary electrons and the secondary holes change the potential of the P-type well or cause a light emission phenomenon, which may cause light to appear in an image, which is naturally not preferable.

Further, when a bipolar transistor is used in the clamp circuit, its output impedance is small, so that a large current flows when the transistor is turned on. Even in a clamp circuit using a MOS transistor, it is usual to lower the output impedance of the clamp MOS transistor from the viewpoint of making it resistant to load fluctuations. Therefore, a voltage lower than the output of the bias circuit is externally applied to expand the dynamic range. If you add, a large current will flow. This is also undesirable.

The present invention has been made to solve the above problems, and applies the output of the built-in bias circuit to a specific portion through the clamp circuit, draws the output terminal of the clamp circuit to the outside, and outputs the terminal. In a solid-state imaging device in which a pulse or signal of a voltage having a large absolute value is applied to the specific portion from the outside through the clamp circuit, the absolute value of the voltage applied from the bias circuit to the specific portion through the clamp circuit is clamped by It is an object of the present invention to make it possible to reduce the current of the constituent diode or transistor without increasing the generation of the current.

[0014]

A semiconductor device according to a first aspect of the present invention is characterized in that an input terminal of a clamp circuit is taken out to the outside. Therefore, according to the semiconductor device of the first aspect, if the means for lowering the absolute value of the potential there is connected to the input terminal of the clamp circuit, the current of the diode or the transistor constituting the clamp circuit is not generated or increased. The absolute value of the output voltage of the clamp circuit can be lowered. Therefore, it is possible to individually adjust the voltage applied to a specific portion of the semiconductor device without the risk of generating secondary electrons and secondary holes in the clamp circuit or causing a large current to flow.

The semiconductor device according to any one of claims 2 to 4 is defined by claim 1.
In the semiconductor device, the load means for reducing the input voltage of the clamp circuit is connected to the input terminal of the clamp circuit. Therefore, according to the semiconductor device of claims 2 to 4, since the voltage on the input side of the clamp circuit can be lowered by the load means, the clamp circuit is not turned on or a large current is not generated. The absolute value of the output voltage of the circuit can be lowered.

According to another aspect of the semiconductor device of the present invention, a diode or a transistor is used as a bias circuit, and a voltage source having a diode or a transistor for canceling the temperature dependence of the diode or the transistor is used as a voltage source for forced voltage application. Is characterized by. Therefore, according to the semiconductor device of the fifth aspect, not only the absolute value of the output voltage of the clamp circuit can be lowered without generating or increasing the current flowing through the clamp circuit, but also the diode forming the clamp circuit is formed. Alternatively, it is possible to prevent the potential of a specific portion from changing due to the temperature dependence of the transistor.

According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, the voltage source is provided with a current limiting resistor for limiting a current passing through the input terminal of the clamp circuit taken out when the power source of the device is turned on. Characterize. Therefore, according to the semiconductor device of the sixth aspect, since the current limiting resistor is provided, the clamp circuit is excessively generated when the power source voltage on the device side rises faster than the power source voltage on the voltage source side when the power source of the device is turned on. It is possible to prevent the problem that a large current flows to the input side of the.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 shows a first embodiment of the present invention. In the figure, 11 is a solid-state imaging device according to one embodiment of the present invention, 1 is a light receiving element arranged in a matrix in a column direction (vertical direction) and a row direction (horizontal direction), and 2 is the light receiving element. In the vertical transfer register provided corresponding to each vertical column 1, the light-receiving element 1 and the vertical transfer register 2 form an imaging area.

Reference numeral 4 denotes a horizontal transfer register which inputs the signal charges transferred from each vertical transfer register 2 in parallel and transfers them in the horizontal direction. Reference numeral 5 denotes a charge detection unit having a floating diffusion structure, which is provided at the output end of the horizontal transfer register 5, 6 is an output amplifier, and 7 is a video signal output terminal. Reference numeral 24 is a timing generator for generating each pulse φV1 to φV4, φH1, φH2 for controlling the solid-state imaging device 11 and the shutter pulse SP, and 25 is a substrate bias generating circuit for generating the substrate bias voltage Vsub.

Reference numeral 36 is a diode forming a clamp circuit,
The output voltage of the substrate bias circuit 25 is the diode 3
The voltage is applied to the semiconductor substrate via 6.
Reference numeral 33 is a terminal for drawing out the cathode of the diode 36 (the anode is connected to the substrate bias circuit 25) to the outside, which serves as a shutter pulse input terminal, and the input terminal 33 receives from the timing generation circuit 24. The shutter pulse SP is input via the capacitor 32. Reference numeral 34 is a resistor connected between the shutter pulse input terminal 33 and the ground.

Reference numeral 37 is a diode 36 forming a clamp circuit.
The first characteristic of the solid-state imaging device 11 is that the solid-state image pickup device 11 has a control terminal 37 on the anode side, that is, a control terminal for extracting the input terminal of the clamp circuit to the outside. Reference numeral 38 denotes a resistor (for example, a variable resistor) connected between the external terminal 37 and the ground. By providing the resistor 38, the output voltage of the substrate bias circuit 25 can be lowered. Then, by changing the resistance 38, it is possible to delicately change the degree to which the input voltage of the clamp circuit 36 is lowered.

Then, the output voltage of the diode 36 can be lowered by the amount that the output voltage of the bias circuit 25 is lowered,
By extension, the substrate bias can be made lower than the value originally set by the manufacturer. Then, the potential profile shown in FIG. 7 can be made shallow and the potential barrier can be increased. Therefore, it is possible to increase the maximum amount of charge that can be accumulated in each light receiving element a, and to extend the dynamic range.

When the shutter pulse SP is input, the diode 36 is naturally cut off because its cathode has a higher potential than its anode. Therefore, the substrate bias circuit 25 and the substrate a are electrically cut off by the diode 36, and the shutter pulse S
The P is transmitted to the substrate a without the bias circuit 25 receiving extra interference. This point is no different from the conventional case.

FIG. 2 is a circuit diagram showing an essential part of the second embodiment of the present invention. In this embodiment, the clamp circuit is composed of a bipolar transistor Q.
Needless to say, a MOS transistor may be used. When the clamp circuit is composed of a transistor, the clamp transistor itself has an amplifying function, so that the output impedance of the substrate bias circuit 25 at the preceding stage can be made relatively large, and the control terminal 37 is extended. The current flowing through the connected load can be made relatively small. That is, the dynamic range can be increased without unnecessarily increasing unnecessary current.

FIG. 3 is a circuit diagram showing an essential part of the third embodiment of the present invention. In this embodiment, the control terminal 3
7, a current source 39 is connected as a load, and a part of the current flowing from the substrate bias circuit 25 to the clamp circuit (for example, the bipolar transistor Q) is robbed by the current source 39 to lower the voltage on the output side of the clamp circuit. The bias of the substrate can be made shallow and the dynamic range can be widened. FIG. 4 is a circuit diagram showing an essential part of the fourth embodiment of the present invention. In this embodiment, a voltage source 40 is connected to the control terminal 37 as a load, and the voltage on the output side of the clamp circuit is lowered by forcibly lowering the potential on the input side of the clamp circuit, thereby making the substrate bias shallower. As a result, the dynamic range can be widened.

FIG. 5 is a circuit diagram showing an essential part of the fourth embodiment of the present invention. In this embodiment, the clamp circuit 38
And a voltage source 40 is used as a load connected to the control terminal 37, and a temperature dependency compensating diode Da for canceling the temperature dependency of the diode D is connected to the voltage source 40. Yes,
When the diode terminal voltage for the same diode current increases due to temperature, for example, due to the temperature dependence of the diode D forming the clamp circuit, the terminal voltage of the temperature compensating diode Da also increases accordingly, and by extension the diode D.
Since the input voltage of is low, the temperature dependence is canceled out. Therefore, it is possible to prevent the potential profile of the solid-state imaging device from changing due to the temperature. This can be applied without any problem even when the clamp circuit is composed of bipolar transistors.

FIG. 6 is a circuit diagram showing an essential part of the fifth embodiment of the present invention. In this embodiment, the clamp circuit is composed of a bipolar transistor (a diode may be used) Q, the voltage source 40 is used as a load connected to the control terminal 37, and the temperature dependency is canceled by the bipolar transistor 43. Further, a current limiting resistor 44 is connected to the collector side of the bipolar transistor 43. 42 is a capacitor. This solid-state image pickup device is intended to eliminate the drawbacks of the embodiment shown in FIG.

The drawback is that in the embodiment of FIG. 5, the solid-state imaging device 11 is faster than the voltage source 40 when the power source voltage rises faster.
There is a possibility that a large current may excessively flow through the clamp diode (or transistor) when the power is turned on. To avoid this, the voltage source should be turned on before the solid-state imaging device when the power supply voltage is turned on, but it is necessary to take special troublesome special measures, which is not practical. . Therefore, in the embodiment of FIG. 6, a current limiting resistor 44 is connected to the collector side of the transistor 43, and even if the power source voltage of the voltage source 40 rises after the solid-state imaging device 11, the current flowing through the transistor 43. Has a resistance of 44
Is restricted by. Therefore, it is possible to prevent a large current from flowing to the load side of the bias circuit 25.

[0029]

According to the semiconductor device of the first aspect, by connecting a means for lowering the absolute value of the potential to the input terminal of the clamp circuit, the generation or increase of the current of the diode or transistor forming the clamp circuit can be achieved. Without this, the absolute value of the output voltage of the clamp circuit can be lowered.
Therefore, it is possible to individually adjust the voltage applied to a specific portion of the semiconductor device without the risk of generating secondary electrons and secondary holes in the clamp circuit or causing a large current to flow.

According to the semiconductor device of the second to fourth aspects, since the voltage on the input side of the clamp circuit can be lowered by the load means, the clamp circuit is not turned on or a large current is not generated. The absolute value of the output voltage of the clamp circuit can be lowered.

According to the semiconductor device of the fifth aspect, not only the absolute value of the output voltage of the clamp circuit can be lowered without generating or increasing the current flowing through the clamp circuit, but also the clamp circuit is formed. It is possible to prevent the potential of a specific portion from changing due to the temperature dependency of the diode or the transistor. According to the semiconductor device of the sixth aspect, since the current limiting resistor is provided, it is possible to prevent a large current from excessively flowing to the input side of the clamp circuit when the device power is turned on.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a main part of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part of a sixth embodiment of the present invention.

FIG. 7 is a potential profile in the depth direction of the solid-state imaging device.

FIG. 8 is a circuit diagram showing a conventional example of a solid-state imaging device.

9A to 9C are circuit diagrams showing another example of a bias circuit.

10A and 10B are circuit diagrams showing another example of the clamp circuit.

[Explanation of symbols]

 11 semiconductor device (solid-state imaging device) 25 bias circuit 36 clamp circuit 37 external terminal (control terminal) 38 load resistance 39 current source for current stealing 40 voltage source 43 temperature-dependent canceling transistor Da temperature-dependent canceling diode Q clamp circuit D clamp circuit

Claims (6)

[Claims] 1. A bias circuit and a clamp circuit for receiving the output thereof are built in, the output of the bias circuit is applied to a specific portion inside the clamp circuit, and the specific portion is electrically taken out to the outside. In a semiconductor device capable of applying a pulse or signal having a voltage whose absolute value is larger than the output voltage of the clamp circuit from the outside to the specific portion through the external terminal, the input terminal of the clamp circuit is taken out to the outside. Semiconductor device characterized by 2. The semiconductor device according to claim 1, wherein a load means for reducing an absolute value of a voltage applied to the input terminal of the clamp circuit taken out to the outside is connected. 3. The semiconductor device according to claim 2, wherein the load means is a voltage source for forced voltage application that reduces the absolute value of the input voltage of the clamp circuit. 4. The semiconductor device according to claim 2, wherein the load means is a current stealing current source that lowers the absolute value of the input voltage of the clamp circuit. 5. A diode or a transistor is used as the bias circuit, and a voltage source having a diode or a transistor for canceling the temperature dependence of the diode or the transistor is used as the voltage source for forced voltage application. 3. The semiconductor device according to 3. 6. The voltage limiting source according to claim 5, wherein a current limiting resistor for limiting a current passing through an input terminal drawn out of the clamp circuit as a load current of the bias circuit when the power source of the apparatus is turned on is connected. Semiconductor device