JP4497261B2 - Charge transfer device, CCD image sensor, and CCD imaging system - Google Patents

Description

[0001]
[Industrial application fields]
The present invention includes a charge transfer device capable of receiving a plurality of charges in parallel and outputting these charges in series, a driving method thereof, a CCD image sensor having the charge transfer device, and the CCD image sensor. The present invention relates to a CCD imaging system.
[0002]
[Prior art]
For example, a charge transfer element can be obtained by forming a strip-shaped n-type channel in a semiconductor substrate and arranging a plurality of electrodes adjacent to each other in parallel via an electrical insulating film on the n-type channel. At this time, the individual electrodes are arranged so as to cross the n-type channel in plan view. Charge transfer devices having an n-type channel can be roughly classified into the following three types.
[0003]
The first type of charge transfer element is a charge transfer element in which the concentration of the n-type impurity in the n-type channel is substantially constant, and the thickness of the electrical insulating film on the n-type channel is also substantially constant.
[0004]
In this type of charge transfer device, the potential well region is relatively low under the electrode to which a relatively high level of voltage is applied, depending on the relative magnitude relationship between the voltages applied to the individual electrodes. A potential barrier region is formed under the electrode to which a level voltage is applied. If a potential barrier region is formed on the upstream side and downstream side of the potential well region, charges can be confined in the potential well region.
[0005]
By appropriately controlling the height of the voltage applied to each electrode, the potential well region sandwiched between the two potential barrier regions can be sequentially moved in a desired direction. The charge can be transferred in a desired direction.
[0006]
In this specification, the movement of the charges transferred by the charge transfer element is regarded as one flow, and the relative positions of the individual members and the like are set to “what upstream”, “ It shall be specified as “downstream” or the like.
[0007]
The second type of charge transfer element is a region in which the concentration of n-type impurities is relatively high (hereinafter, this region is referred to as “n”⁺This is referred to as a “type impurity doped region”. ) And a relatively low region (hereinafter, this region is referred to as an “n-type impurity doped region”) is a charge transfer element formed alternately in an n-type channel.
[0008]
In this type of charge transfer device, typically n⁺One electrode is disposed on each of the impurity doped region and the n doped region via an electrical insulating film. An electrode disposed on one n-type impurity doped region and n on the downstream side thereof⁺The electrode arranged on the type impurity added region is connected in common. One n-type impurity doped region and n downstream thereof⁺One electrode covering the type impurity doped region may be formed on these regions.
[0009]
Individual n⁺The type impurity doped region is always a potential well region with respect to the n type impurity doped region. The charge in the potential well region is prohibited from moving by the potential barrier region. Charges can be transferred in the direction from the potential barrier region to the potential well region.
[0010]
This will be described more specifically. A certain n⁺Type impurity doped region⁺N-type impurity added region A ”, an n-type impurity added region immediately downstream thereof is referred to as“ n-type impurity added region B ”, and an n-type impurity added region B immediately downstream of“ n-type impurity added region B ”⁺Type impurity doped region⁺Type impurity doped region C ". On the regions B and C, electrodes connected in common are arranged.
[0011]
n⁺When charge is distributed in the type impurity doped region A (potential well region), the n type impurity doped region B, n⁺When a relatively high voltage is applied to the electrode on the type impurity doped region C, the n type impurity doped region B becomes n⁺It does not function as a potential barrier region for the type impurity doped region A. n⁺The type impurity doped region C is always a potential well region with respect to the n type impurity doped region B. Therefore, n⁺The charge distributed in the type impurity doped region A is n through the n type impurity doped region B.⁺It moves to the type impurity addition region C.
[0012]
The n-type impurity doped region B is n⁺It functions as a potential barrier region for the type impurity doped region C. n-type impurity doped region B, n⁺Even if the voltage applied to the electrode on the type impurity doped region C is restored to the original level, n⁺The charge transferred to the type impurity doped region C is n⁺There is no return to the type impurity added region A.
[0013]
In the third type of charge transfer device, the n-type impurity concentration in the n-type channel is substantially constant, and the electrically insulating film on the n-type channel is a relatively thick region (hereinafter referred to as “ This is a charge transfer device in which relatively thick regions (hereinafter sometimes referred to as “thin regions”) and alternately thin regions (hereinafter sometimes referred to as “thin regions”).
[0014]
Usually, one electrode is disposed on each of the thick and thin regions. The electrode arranged on one thin area and the electrode arranged on the thick area on the downstream side thereof are connected in common. One electrode that covers one thin region and a thick region downstream thereof may be formed on these regions.
[0015]
In this type of charge transfer device, even when a constant voltage is applied to each electrode, when the n-type channel is a buried channel, the potential barrier region is formed below the thin region and the potential well region is formed below the thick region. Is formed. Charges can be transferred in the direction from the potential barrier to the potential well.
[0016]
As a representative electronic device using a charge transfer element, there is a CCD (Charge Coupled Element) image sensor. It can be roughly divided into a CCD linear (line) image sensor and a CCD area image sensor.
[0017]
A CCD area image sensor usually includes two types of charge transfer elements. One is a charge transfer element called VCCD or vertical charge transfer element, and the other is a charge transfer element called HCCD or horizontal charge transfer element.
[0018]
In the interline CCD area image sensor, a large number of photoelectric conversion elements are arranged in a matrix over a plurality of rows and columns, and one VCCD is arranged for each photoelectric conversion element column. In many CCD area image sensors, each VCCD is electrically connected to one HCCD. A CCD area image sensor having a plurality of HCCDs is also known.
[0019]
The VCCD is generally constituted by a charge transfer element of a type in which the concentration of the n-type impurity in the n-type channel is substantially constant and the thickness of the electrical insulating film on the n-type channel is also substantially constant. This charge transfer element (VCCD) is usually driven by vertical drive signals of three or more phases. In each VCCD, one vertical charge transfer stage is constituted by one electrode and a region of the n-type channel located under this electrode. About 2 to 4 vertical charge transfer stages are arranged for one photoelectric conversion element.
[0020]
In HCCD, for example, n type channel has n⁺Type impurity doped regions and n type impurity doped regions are alternately formed, and a commonly connected electrode is disposed on a pair of adjacent impurity doped regions. One horizontal charge transfer stage is constituted by a pair of adjacent impurity-added regions and a commonly connected electrode thereon. Two horizontal charge transfer stages are arranged for one VCCD. This charge transfer element (HCCD) is normally driven by a two-phase horizontal drive signal.
[0021]
A CCD imaging system such as an electronic still camera has been developed using a CCD area image sensor.
[0022]
The electronic still camera includes a small monitor and is configured so that a user can select a still image recording mode for recording a still image and a monitor mode for displaying an image on a small monitor. The monitor mode is used, for example, when the user determines the angle of view of a still image.
[0023]
In recent years, the number of pixels of still images picked up by an electronic still camera has reached several million, and more than six million. On the other hand, the number of pixels when displaying a moving image in the monitor mode of an electronic still camera is generally about 100,000 to 400,000.
[0024]
For this reason, in the monitor mode, the photoelectric conversion elements from which charges are read out to the VCCD are limited to some photoelectric conversion element rows. Thinning scanning is performed to read out charges by thinning photoelectric conversion element rows to 1/2 or more. Alternatively, charges are mixed (vertical addition) within each VCCD. That is, the charges accumulated in each of the two or more photoelectric conversion elements adjacent to each other in the photoelectric conversion element column direction are mixed (vertically added) in the VCCD corresponding to the photoelectric conversion element column. . If charges are added, the amount of signal (charge) handled as one pixel in signal processing increases, so that an advantage that the imaging sensitivity increases in accordance with the amount of addition can be obtained. Relatively bright images can be reproduced.
[0025]
In a CCD imaging system for color imaging, a color filter array is used to obtain full color information. The color filter array is composed of color filters of a plurality of colors arranged under a fixed repeating pattern, and one color filter corresponds to one photoelectric conversion element.
[0026]
[Problems to be solved by the invention]
In a conventional CCD imaging system, charges can be mixed (vertical addition) in the VCCD by appropriately selecting the waveform of the vertical drive signal.
[0027]
However, an HCCD that can perform charge mixing (horizontal addition) has not yet been proposed.
[0028]
When image data is generated based on an image signal obtained by performing vertical charge addition in the VCCD and not performing horizontal charge addition in the HCCD, only the number of vertical pixels is thinned out. If charges can be added by both VCCD and HCCD, it becomes easy to obtain a better reproduced image.
[0029]
An object of the present invention is to provide a charge transfer device that facilitates the addition of desired charges.
[0030]
Another object of the present invention is to provide a method for driving a charge transfer device that facilitates the addition of desired charges.
[0031]
Yet another object of the present invention is to provide a CCD image sensor that facilitates the addition of the desired charge both in the VCCD and in the HCCD.
[0032]
Still another object of the present invention is to provide a CCD imaging system capable of obtaining image data by adding desired charges in both the VCCD and the HCCD.
[0033]
[Means for Solving the Problems]
  According to an aspect of the present invention, a semiconductor substrate, N first charge transfer channel regions of a first conductivity type formed on one surface of the semiconductor substrate, and the first charge formed on the semiconductor substrate. A charge transfer element including a second charge transfer channel of a first conductivity type electrically connected to each of the transfer channel regions,A plurality of charge transfer stages arranged in a row corresponding to each of the first charge transfer channel regions can be formed, and each of the charge transfer stages has only one first A potential barrier region and only one first potential well region;At least one transfer electrode formed on the second charge transfer channel with an electrical insulating film corresponding to each of the first charge transfer channel regions, the N transfer electrodes Is composed of a plurality of groups in which m consecutive (m represents an integer of 3 or more) is taken as one group, and n (n represents a positive integer of m or less) among the m transfer electrodes. .) Are each connected to an electrically independent voltage supply line, and each charge transfer element having a period of m is connected to the same voltage supply line,Each of the charge transfer stages formed in the connection region has a configuration in which at least one charge transfer stage can be formed in a connection region between each of the first charge transfer channel regions and the charge transfer element. A line memory having one second potential barrier region and one second potential well region formed on the second charge transfer channel side of the second potential barrier region; the line memory; and A drive circuit capable of generating a drive signal or a control signal supplied to each charge transfer element, wherein a charge corresponding to a desired first charge transfer channel region is selectively selected from the line memory. Drive circuit to transfer toIs provided.
[0035]
  Of the present inventionotherAccording to an aspect, (i) a semiconductor substrate, (ii) N first charge transfer channel regions of a first conductivity type formed on one surface of the semiconductor substrate, and (iii) formed on the semiconductor substrate. A charge transfer element including a first conductivity type second charge transfer channel electrically connected to each of the first charge transfer channel regions,A plurality of charge transfer stages arranged in a row corresponding to each of the first charge transfer channel regions can be formed, and each of the charge transfer stages has only one first A potential barrier region and only one first potential well region;At least one transfer electrode formed on the second charge transfer channel with an electrical insulating film corresponding to each of the first charge transfer channel regions, the N transfer electrodes Is composed of a plurality of groups in which m consecutive (m represents an integer of 3 or more) is taken as one group, and n (n represents a positive integer of m or less) among the m transfer electrodes. .) Are each connected to an electrically independent voltage supply line, and each charge transfer element having a period of m is connected to the same voltage supply line,(iv) A charge transfer stage formed in the connection region, wherein at least one charge transfer stage can be formed in a connection region between each of the first charge transfer channel regions and the charge transfer element. Each line memory having one second potential barrier region and one second potential well region formed on the second charge transfer channel side of the second potential barrier region, and (v ) A drive circuit capable of generating a drive signal or a control signal supplied to each of the line memory and the charge transfer element, wherein a charge corresponding to a desired first charge transfer channel region is selected from the line memory. A drive circuit for transferring to the charge transfer device in general,A method of driving a charge transfer device comprising:Line memoryA step of selectively transferring a charge from a part of the charge transfer element to the charge transfer element, a step of transferring at least a part of the charge transferred to the charge transfer element downstream in the charge transfer element, and the charge For at least part of the charge transferred in the transfer element,Line memoryAnd adding a charge from the charge transfer device, wherein m / 2 or less charges per m of the first charge transfer channel regions are distributed in the charge transfer element.
[0036]
  According to still another aspect of the present invention, a semiconductor substrate, a plurality of photoelectric conversion elements formed in a matrix over a plurality of rows and columns on one surface of the semiconductor substrate, and each of the photoelectric conversion element columns A plurality of vertical charge transfer elements formed on the semiconductor substrate so as to extend along the photoelectric conversion element array, and at least one charge transfer stage downstream of each of the vertical charge transfer elements. A CCD line memory unit that can be formed one by one, wherein each of the charge transfer stages includes a first charge transfer channel region of a first conductivity type following a corresponding vertical charge transfer element; A first conductivity type horizontal charge transfer channel formed on a semiconductor substrate and electrically connected to each of the first charge transfer channel regions, and an electrical insulating film above the horizontal charge transfer channelA horizontal charge transfer device having at least N horizontal transfer electrodes formed corresponding to each of the first charge transfer channel regions, wherein the N horizontal transfer electrodes are continuous. m (m represents an integer of 3 or more) is composed of a plurality of groups, and n of the m horizontal transfer electrodes (n represents a positive integer of m or less). Each of the horizontal charge transfer elements is connected to an electrically independent voltage supply line, and each of the horizontal transfer electrodes having a period of m is connected to the same voltage supply line. Each of the horizontal charge transfer stages has a configuration capable of forming a plurality of horizontal charge transfer stages arranged in a row corresponding to each one, and each of the horizontal charge transfer stages includes only one first potential barrier region, Only one first potential well area Each of the vertical charge transfer element, the CCD line memory unit, and the horizontal charge transfer element. A drive circuit for selectively transferring a charge corresponding to the desired first charge transfer channel region from the CCD line memory section to the horizontal charge transfer element;WithThe CCD line memory unit includes one second potential barrier region, one second potential well region formed on the second charge transfer channel side of the second potential barrier region, and the second potential barrier region. A potential barrier region and a transfer control electrode disposed above the second potential well regionCCD image sensor.
[0038]
By configuring the CCD image sensor as described above, the following advantages can be obtained. That is, a plurality of first charge transfer channel regions electrically connected to the horizontal charge transfer element are divided into a plurality of groups, and the horizontal charge is selectively selectively group by group from the first charge transfer channel region and thus from the vertical charge transfer element. Charges can be transferred to the transfer element.
[0039]
If charges can be selectively transferred from the first charge transfer channel region to the horizontal charge transfer device, the two charges transferred from the two first charge transfer channel regions belonging to different groups to the horizontal charge transfer device can be easily obtained. Can be added (mixed).
[0040]
For example, after transferring the charge transferred from the first charge transfer channel region belonging to one group to the horizontal charge transfer element to below the predetermined horizontal transfer electrode corresponding to the first charge transfer channel region belonging to the other group, By transferring charges from the first charge transfer channel belonging to another group to the horizontal charge transfer element, the two charges can be horizontally added at this point. Desired charges can be easily added in the horizontal charge transfer element.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram illustrating an outline of a CCD imaging system according to an embodiment. As shown in the figure, the CCD imaging system 100 according to the present embodiment includes an imaging optical system 1, a CCD image sensor 10, a drive circuit 65, a video signal processing circuit 70, an image data output unit 75, a display unit 80, and a recording unit 82. , A control unit 85, a mode selector 90, and a pulse signal generation unit 95.
[0042]
The imaging optical system 1 forms an optical image on the CCD image sensor 10. The imaging optical system 1 includes, for example, an optical lens, a diaphragm, an optical low-pass filter, and the like. Arrow L in the figure indicates light.
[0043]
The CCD image sensor 10 converts an optical image formed by the imaging optical system 1 into an electrical signal. The CCD image sensor 10 includes a photoelectric conversion element, a vertical charge transfer element (VCCD), a horizontal charge transfer element (HCCD), an output unit, and a color filter array. Details of the CCD image sensor 10 will be described later.
[0044]
The drive circuit 65 supplies drive signals and control signals necessary for the operation of the CCD image sensor 10 to the CCD image sensor 10. The drive circuit 65 includes, for example, a vertical driver, a horizontal driver, a DC power source, and the like.
[0045]
The video signal processing circuit 70 receives the image signal generated by the CCD image sensor 10 and performs various processes on the image signal to generate image data. The video signal processing circuit 70 includes, for example, an analog / digital converter, a CDS circuit (correlated double sampling circuit), a color separation circuit, a delay line, and the like.
[0046]
The image data output unit 75 receives the image data output from the video signal processing circuit 70 and stores the image data in a storage medium such as a frame memory, for example.
[0047]
The display unit 80 displays a still image or a moving image based on the image data supplied from the image data output unit 75. The display unit 80 includes a display device such as a liquid crystal display.
[0048]
The recording unit 82 records the image data supplied from the image data output unit 75 on a recording medium such as a memory card.
[0049]
The control unit 85 controls operations of the drive circuit 65, the video signal processing circuit 70 and the image data output unit 75. The control unit 85 is constituted by, for example, a central processing unit (CPU).
[0050]
The mode selector 90 is a selection switch for selecting an imaging mode of the CCD imaging system 100. The CCD imaging system 100 has, for example, at least two imaging modes, that is, a still image recording mode in which a still image is captured and recorded, and a monitor mode in which a moving image or a still image is captured and displayed on the display unit 80. The mode selector 90 is operated by a user of the CCD imaging system 100.
[0051]
The pulse signal generation circuit 95 generates a pulse signal for unifying the operation timing in the apparatus, and supplies the pulse signal to the drive circuit 65, the video signal processing circuit 70, and the control unit 85. The pulse signal generation circuit 95 includes, for example, an original oscillation that generates pulses at a constant cycle, a timing generator, and the like.
[0052]
The CCD image sensor 10 constituting the CCD imaging system 100 is a CCD image sensor that can vertically and horizontally add charges accumulated in a plurality of photoelectric conversion elements in the CCD image sensor 10. Hereinafter, the configuration of the CCD image sensor 10 will be described with reference to examples.
[0053]
FIG. 2 is a sectional view schematically showing a photoelectric conversion element and its periphery in the CCD image sensor 10a according to the first embodiment. In the same figure, a total of three photoelectric conversion elements 15 including those partially shown are shown.
[0054]
In the CCD image sensor 10 a shown in FIG. 2, a photoelectric conversion element 15 is formed on one surface of the semiconductor substrate 11. The semiconductor substrate 11 includes an n-type semiconductor substrate 11a such as silicon and a p-type impurity doped region 11b formed thereon.
[0055]
In the photoelectric conversion element 15, for example, an n-type impurity addition region 15a is provided at a predetermined position of the p-type impurity addition region 11b, and the p-type impurity addition region 15a has a p⁺ This is a buried photodiode formed by providing a type impurity doped region 15b. Each of the n-type impurity added regions 15a functions as a charge storage region.
[0056]
On the right side of each photoelectric conversion element 15 in FIG. 2, one vertical charge transfer channel 20 a having a width of about 0.3 to 5 μm is arranged close to each other. Each vertical charge transfer channel 20a has an n-type channel formed by providing an n-type impurity doped region at a predetermined position of the p-type impurity doped region 11b as a basic structure. P on the addition region^- It includes a region where a type impurity doped region is formed.
[0057]
A p-type impurity addition region 11b is exposed one by one along the right edge in FIG. 2 in each photoelectric conversion element 15 (n-type impurity addition region 15a). This region in the p-type impurity doped region 11b is used as a read gate channel region 21a. Each of the read gate channel regions 21a extends from substantially the center of the right edge of the corresponding photoelectric conversion element 15 to the downstream end thereof in plan view. The vertical charge transfer channel 20a and the photoelectric conversion element 15 corresponding thereto are adjacent to each other through the read gate channel region 21a.
[0058]
The channel stop region 22 surrounds the periphery of each photoelectric conversion element 15 in plan view, except for the portion where the read gate channel region 21a is formed. The channel stop region 22 electrically isolates the photoelectric conversion elements 15 from each other, and the photoelectric conversion elements 15 and the vertical charge transfer channel 20a not corresponding thereto. The width of the channel stop region 22 formed between the photoelectric conversion element 15 and the vertical charge transfer channel 20a in plan view is, for example, about 0.5 μm.
[0059]
Further, further downstream than the most downstream photoelectric conversion element row, channel stop regions 22 are also formed around the vertical charge transfer channels 20a in plan view. The channel stop region 22 is formed, for example, at a predetermined position of the p-type impurity added region 11b.⁺ It is formed by providing a type impurity doped region.
[0060]
Each impurity added region can be formed by, for example, ion implantation and subsequent annealing. The p-type impurity doped region 11b can also be formed by, for example, an epitaxial growth method. p⁺ The p-type impurity concentration in the p-type impurity addition region is higher than the p-type impurity concentration in the p-type impurity addition region. p^- The p-type impurity concentration in the p-type impurity addition region is lower than the p-type impurity concentration in the p-type impurity addition region.
[0061]
The electrically insulating film 25 having a substantially constant film thickness includes one surface of the semiconductor substrate 11, that is, the surface on the side where the above-described various impurity-added regions are formed (including the surfaces of various impurity-added regions). ) Is formed on.
[0062]
The electrically insulating film 25 is formed using, for example, an electrically insulating oxide such as silicon oxide, or an electrically insulating nitride such as silicon nitride. This electrical insulating film 25 is, for example, a single layer structure composed of one electrically insulating oxide layer, a two-layer laminated structure of an electrically insulating oxide layer and an electrically insulating nitride layer formed thereon, Alternatively, it has a three-layer structure of an electrically insulating oxide layer, an electrically insulating nitride layer formed thereon, and an electrically insulating oxide layer formed thereon.
[0063]
First to second vertical transfer electrodes 31 to 32, first to third auxiliary transfer electrodes 33 to 35, first to second transfer control electrodes 41 to 42, and first to second horizontal transfer electrodes 47 to 48. Is formed on the electrical insulating film 25. However, only the first vertical transfer electrode 31 is visible in FIG. Each electrode not shown in FIG. 2 will be described in detail later with reference to FIG. 4 or FIG.
[0064]
Each of the electrodes 31 to 32, 33 to 35, 41 to 42, and 47 to 48 is individually covered with an electrical insulating film (thermal oxide film) 50.
[0065]
One region of the first vertical transfer electrode 31 covers one region of the vertical charge transfer channel 20a in plan view, and constitutes a vertical charge transfer element (VCCD) 20 together with this one region. The other region of the first vertical transfer electrode 31 covers the read gate channel region 21a in plan view and constitutes the read gate 21 together with the read gate channel region 21a.
[0066]
When a read pulse, which will be described later, is applied to the first vertical transfer electrode 31, a p-type channel is induced in the read gate 21 (read gate channel region 21a), corresponding to the photoelectric conversion element 15 (n-type impurity doped region 15a). To the vertical charge transfer channel 20a.
[0067]
The light shielding film 51 covers the electrical insulating film 25 and various electrodes formed thereon. However, the light shielding film 51 is provided with the photoelectric conversion element 15 (p⁺ One open portion 51a having a predetermined shape is provided on each of the type impurity addition regions 15b). Each opening 51a is open on the inner side in a plan view than the outer peripheral surface of the n-type impurity addition region 15a in the photoelectric conversion element 15.
[0068]
The light shielding film 51 includes a thin film made of a metal such as aluminum, chromium, tungsten, titanium, and molybdenum, an alloy thin film made of two or more of these metals, or the metal thin film and the alloy thin film. It is formed by a multilayer metal thin film or the like that is a combination of two or more selected from the group.
[0069]
A protective film 52 is formed on the light shielding film 51 and on the electrical insulating film 25 exposed from the opening 51a. The protective film 52 is formed of, for example, silicon nitride, silicon oxide, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), polyimide, or the like.
[0070]
The first planarization film 53 covers the protective film 52. The first planarization film 53 is also used as a focus adjustment layer for a microlens. An inner lens is formed in the first planarization film 53 as necessary.
[0071]
The first planarization film 53 is formed by applying a transparent resin such as a photoresist to a desired thickness by, for example, a spin coating method.
[0072]
A color filter array 55 is formed on the first planarization film 53. The color filter array 55 is formed by forming a plurality of types of color filters with a predetermined pattern that enables color imaging. As color filter arrays for color imaging, there are a primary color filter array and a complementary color filter array.
[0073]
In each of the primary color filter array and the complementary color filter array, one color filter is disposed above each photoelectric conversion element 15. The arrangement pattern of the color filters in the illustrated color filter array 55 will be described in detail later with reference to FIG. In FIG. 2, one red filter 55R, one green filter 55G, and one blue filter 55B are shown.
[0074]
The color filter array 55 can be produced, for example, by forming a resin (color resin) layer containing a pigment or dye of a desired color at a predetermined position by a method such as photolithography.
[0075]
A second planarizing film 56 is formed on the color filter array 55. The second planarizing film 56 is formed by applying a transparent resin such as a photoresist to a desired thickness by, for example, a spin coating method.
[0076]
A microlens array 58 is formed on the second planarization film 56. The microlens array 58 is constituted by microlenses 58 a arranged one by one above the individual photoelectric conversion elements 15.
[0077]
These microlenses 58a are formed by, for example, partitioning a layer made of a transparent resin (including a photoresist) having a refractive index of approximately 1.3 to 2.0 into a predetermined shape by a photolithography method or the like, and then performing a heat treatment to each partition. The transparent resin layer is melted, the corners are rounded by surface tension, and then cooled.
[0078]
FIG. 3 is a plan view showing a part of the color filter array 55. In the figure, for convenience, a red filter is indicated by a symbol R, a green filter is indicated by a symbol G1 or G2, and a blue filter is indicated by a symbol B.
[0079]
In the color filter array 55 shown in the figure, the first color filter row FC1 constituted only by the green filter G1, the second color filter row FC2 constituted solely by the red filter R, and the green filter G2 alone are constituted. In addition, the third color filter row FC3 and the fourth color filter row FC4 configured by only the blue filter B are repeatedly arranged in this order from the left to the right of the drawing.
[0080]
The green color filter G1 constituting the first color filter row FC1 and the green color filter G2 constituting the third color filter row FC3 are simply made by changing reference numerals for convenience, and both are formed of the same material. .
[0081]
In addition, the area | region enclosed with the broken line shown in each color filter in FIG. 3 shows the outline of the photoelectric conversion element area | region 16 mentioned later.
[0082]
FIG. 4 is a partial plan view schematically showing the CCD image sensor 10a. However, the light shielding film 51, the protective film 52, the first planarizing film 53, the second planarizing film 56, and the microlens array 58 shown in FIG. Although illustration of the color filter array 55 itself is omitted, the color of the color filter arranged on each photoelectric conversion element 15 is indicated by symbols G1, G2, R, or B. The meanings of symbols G1, G2, R, and B are the same as those in FIG. Among the components shown in FIG. 4, the components already shown in FIG. 2 are denoted by the same reference symbols as those used in FIG.
[0083]
As shown in FIG. 4, in the CCD image sensor 10a, a large number of photoelectric conversion elements 15 are arranged in a matrix over a plurality of rows and columns on a semiconductor substrate 11. The number of photoelectric conversion elements 15 shown in the figure is 30, except for those that are partially visible. In an actual CCD image sensor, the total number of photoelectric conversion elements 15 exceeds several million, for example. The pitch of the photoelectric conversion elements in the photoelectric conversion element column direction and the photoelectric conversion element row direction is appropriately selected within a range of 2 to 10 μm, for example.
[0084]
One vertical charge transfer channel 20a is disposed adjacent to one photoelectric conversion element array along the right side (the right side in FIG. 4).
[0085]
The first to second vertical transfer electrodes 31 to 32 are arranged one by one in one photoelectric conversion element row. Each of the first vertical transfer electrodes 31 extends downstream along the corresponding photoelectric conversion element row while intersecting with each vertical charge transfer channel 20a in plan view. Each of the second vertical transfer electrodes 32 extends to the upstream side along the corresponding photoelectric conversion element row while intersecting each vertical charge transfer channel 20a in plan view.
[0086]
Each first vertical transfer electrode 31 constitutes one read gate 21 together with one read gate channel region 21a (see FIG. 2) on the right side of each corresponding photoelectric conversion element 15 in FIG. FIG. 2 schematically shows an enlarged cross-sectional view taken along the line II-II shown in FIG.
[0087]
The first to second vertical transfer electrodes 31 to 32 corresponding to one photoelectric conversion element row are the photoelectric conversion elements 15 in the photoelectric conversion element row except for the photoelectric conversion elements 15 included in the leftmost photoelectric conversion element column. Are surrounded by a plan view to define a photoelectric conversion element region 16.
[0088]
The first to third auxiliary transfer electrodes 33 to 35 are arranged one by one in this order on the downstream side of the most downstream first vertical transfer electrode 31. Each of these first to third auxiliary transfer electrodes 33 to 35 also extends in the photoelectric conversion element row direction while intersecting with each vertical charge transfer channel 20a in plan view.
[0089]
The first to second transfer control electrodes 41 to 42 are arranged in this order on the downstream side of the third auxiliary transfer electrode 35. These first to second transfer control electrodes 41 to 42 also extend in the photoelectric conversion element row direction while intersecting each vertical charge transfer channel 20a in plan view.
[0090]
The second vertical transfer electrode 32, the first auxiliary transfer electrode 33, the third auxiliary transfer electrode 35, and the second transfer control electrode 42 are formed by a first polysilicon layer provided at the first level on the semiconductor substrate 11. . The first vertical transfer electrode 31, the second auxiliary transfer electrode 34, and the first transfer control electrode 41 are formed by a second polysilicon layer provided at a second level above the first level on the semiconductor substrate 11. . The individual electrodes 31 to 35 and 41 to 42 are covered with the electrical insulating film (thermal oxide film) 50 (see FIG. 2) as described above.
[0091]
In each of the vertical charge transfer channels 20a, a region facing the first vertical transfer electrode 31, the second vertical transfer electrode 32, the first auxiliary transfer electrode 33, the second auxiliary transfer electrode 34, or the third auxiliary transfer electrode 35 is Together with the upper electrode 31, 32, 33, 34 or 35, one vertical charge transfer stage is constituted. The first to second vertical transfer electrodes 31 to 32 and the first to third auxiliary transfer electrodes 33 to 35 constitute one vertical charge transfer stage with each of the vertical charge transfer channels 20a.
[0092]
Each of the vertical charge transfer stages configured to include one vertical charge transfer channel 20a constitutes one vertical charge transfer element 20 connected in the photoelectric conversion element array direction. Of the individual vertical charge transfer channels 20a, the region constituting the vertical charge transfer element 20 is constituted by an n-type channel.
[0093]
On the other hand, the regions facing the first transfer control electrode 41 and the second transfer control electrode 42 in each of the vertical charge transfer channels 20a constitute one charge transfer stage 40a together with the transfer control electrodes 41 and 42 thereon. The charge transfer stage 40a is hereinafter referred to as “transfer control stage 40a”.
[0094]
Two pairs of the first to second transfer control electrodes 41 to 42 constitute a pair, and constitute one transfer control stage 40a with each of the vertical charge transfer channels 20a. These transfer control stages 40a constitute one CCD line memory section 40 as a whole. The configuration of the vertical charge transfer channel 20a in the CCD line memory section 40 will be described in detail later with reference to FIG.
[0095]
The downstream end of each vertical charge transfer channel 20 a (the downstream end of the first charge transfer channel region) is electrically connected to a horizontal charge transfer element (HCCD) 45.
[0096]
An output unit 60 is connected to one end of the horizontal charge transfer element 45. The output unit 60 is connected to the downstream end of the horizontal charge transfer element 45. The output unit 60 converts the charge sent from the horizontal charge transfer element 45 into a signal voltage using, for example, a floating capacitor (not shown), and uses the signal voltage using a source follower circuit (not shown). Amplify. The charge of the floating capacitance after being detected (converted) is absorbed by a power supply (not shown) through a reset transistor (not shown). The output unit 60 can be configured in the same manner as the output unit described with reference to FIG. 4B in the 0084th to 0091th stages of Japanese Patent Application No. 11-287332, for example.
[0097]
Hereinafter, the configurations of the line memory unit 40 and the horizontal charge transfer element 45 will be described in detail with reference to FIGS. 5, 6A, and 6B.
[0098]
FIG. 5 is a schematic diagram showing an enlarged area from the CCD line memory unit 40 to the horizontal charge transfer element 45.
[0099]
6A is a schematic view of a cross section taken along line VIA-VIA shown in FIG. 5, and FIG. 6B is a schematic view of a cross section taken along line VIB-VIB shown in FIG. is there.
[0100]
As shown in FIG. 6A, the downstream end of each of the vertical charge transfer channels 20 a is in contact with the horizontal charge transfer channel 46.
[0101]
Each of the vertical charge transfer channels 20a in the CCD line memory section 40 is formed on the n-type impurity doped region (n-type channel) 20a1 by p.^-  It has one potential barrier region 20B in which the type impurity doped region 20a2 is formed and one potential well region 20W constituted only by the n type impurity doped region (n type channel) 20a1.
[0102]
The width of the potential barrier region 20B (width in the photoelectric conversion element column direction) is, for example, about 0.5 to 1 μm, and the width of the potential well region 20W (width in the photoelectric conversion element column direction) is, for example, 2 to 20 μm. Degree. In any region, the conductivity type as a charge transfer channel is n-type.
[0103]
Each of the potential barrier regions 20B is covered with the first transfer control electrode 41 via the electrical insulating film 25. Each of the potential well regions 20 </ b> W is covered with the second transfer control electrode 42 through the electrical insulating film 25.
[0104]
The first transfer control electrode 41 is disposed above the potential / barrier region 20B via the electrical insulating film 25. The second transfer control electrode 42 is disposed above the potential / well region 20 </ b> W via the electrical insulating film 25. For example, the second transfer control electrode 42 is formed by the first polysilicon layer, and the first transfer control electrode 41 is formed by the second polysilicon layer.
[0105]
Each transfer control stage 40a is composed of one potential barrier region 20B, a first transfer control electrode 41 thereabove, one potential well region 20W, and a second transfer control electrode 42 thereabove. The
[0106]
The first transfer control electrode 41 and the second transfer control electrode 42 are connected in common and receive the supply of the control signal φLM. By controlling the level of the control signal φLM to increase the potential of the potential barrier region 20B, it becomes possible to transfer charges from the vertical charge transfer element 20 to the transfer control stage 40a. By controlling the level of the control signal φLM to lower the potential of the potential / well region 20W, charges can be transferred from the transfer control stage 40a to the horizontal charge transfer element 45.
[0107]
The charge transfer from the transfer control stage 40a to the horizontal charge transfer element 45 will be described in detail later with reference to FIGS. 9 (A) and 9 (B).
[0108]
As shown in FIG. 5, the horizontal charge transfer element 40 includes one horizontal charge transfer channel 41 extending in a strip shape in the photoelectric conversion element row direction, and a large number of second charge transfer channels 41 formed on the horizontal charge transfer channel 41. First to second horizontal transfer electrodes 42 to 43.
[0109]
As shown in FIGS. 6A and 6B, the horizontal charge transfer channel 46 is formed on the n-type impurity doped region (n-type channel) 46a.^-  It has a potential barrier region 46B in which a type impurity doped region 46b is formed, and a potential well region 46W constituted only by an n type impurity doped region (n type channel) 46a. In any of the regions 46B and 46W, the conductivity type as a charge transfer channel is n-type.
[0110]
The potential barrier region 46B extends from the first barrier region 46B1 extending in a strip shape in the photoelectric conversion element row direction, and from the first barrier region 46B1 at a constant interval, and extends in a strip shape in the photoelectric conversion element column direction. A plurality of second barrier regions 46B2. One potential well region 46W adjacent to one second barrier region 46B2 and the second barrier region 46B2 downstream thereof is formed. One potential well region 46W is also formed on the downstream side of the most downstream second barrier region 46B2.
[0111]
The first barrier region 46B1 separates the transfer control stage 40a from the potential / well region 46W in the horizontal charge transfer element 45. Each of the second barrier regions 46B2 separates the potential / well regions 46W from each other in the horizontal charge transfer element 45.
[0112]
Each first horizontal transfer electrode 47 covers one second barrier region 46B2 and the first barrier region 46B1 following the second barrier region 46B2. The first horizontal transfer electrode 47 has an inverted L shape in plan view (see FIG. 5).
[0113]
Each second horizontal transfer electrode 48 covers one potential well region 46W. The second horizontal transfer electrode 48 has a rectangular shape in plan view (see FIG. 5).
[0114]
The first and second horizontal transfer electrodes 47 and 48 are formed on the semiconductor substrate 1 with the electrical insulating film 23 interposed therebetween. For example, the second horizontal transfer electrode 48 is formed by the second polysilicon layer, and the first horizontal transfer electrode 47 is formed by the third polysilicon layer.
[0115]
One first horizontal transfer electrode 47, a potential barrier region 46B below it, one second horizontal transfer electrode 48, and a potential well region 46W therebelow are one horizontal charge transfer stage 45a. Alternatively, the auxiliary horizontal charge transfer stage 45b is configured. One horizontal charge transfer stage 45a has only one potential barrier region and only one potential well region.
[0116]
The horizontal charge transfer stages 45a are formed in a row corresponding to one vertical charge transfer channel 20a. A total of three auxiliary horizontal charge transfer stages 45b are formed on the downstream side of the horizontal charge transfer stage 40a corresponding to the leftmost vertical charge transfer channel 20a in FIG. 5 (which means the output unit 60 side described later). ing.
[0117]
The first and second horizontal transfer electrodes 47 and 48 constituting one horizontal charge transfer stage or auxiliary horizontal charge transfer stage are connected in common and supplied with a horizontal drive signal φH1, φH2 or φH3.
[0118]
When transferring charges from the transfer control stage 40a to the horizontal charge transfer element 45, the levels of the control signal φLM and the horizontal drive signals φH1, φH2 or φH3 are controlled as follows, for example. That is, the potential of the potential barrier region 46B in the horizontal charge transfer stage 45a is controlled to be relatively higher than the potential of the potential well region 20W in the transfer control stage 40a. Charges can be transferred from the transfer control stage 40a to the horizontal charge transfer element 45. The principle of charge transfer from the transfer control stage 40a to the horizontal charge transfer element 45 will be described in detail later with reference to FIGS. 9 (A) and 9 (B).
[0119]
When charges are transferred in the horizontal charge transfer element 45, the levels of the horizontal drive signals φH1 to φH8 are controlled as follows, for example. That is, the potential of the potential well region 20W in the horizontal charge transfer stage 40a in which charges are distributed is controlled to be relatively lower than the potential of the potential barrier region 46B in the horizontal charge transfer stage 40a downstream thereof. The
[0120]
As shown in FIG. 6B, a channel stop 22 is arranged around each vertical charge transfer channel 20a in plan view, except for a portion adjacent to the horizontal charge transfer channel 46. As shown in FIGS. 6A and 6B, the photoelectric conversion element row direction is also provided on the outer peripheral portion of the horizontal charge transfer channel 46 in the photoelectric conversion element column direction (however, away from the vertical charge transfer channel 20a). A channel stop 22 is arranged so as to extend in the direction.
[0121]
The CCD image sensor 10a having the configuration described above is driven in accordance with the drive signal and control signal supplied from the drive circuit 65 (see FIG. 1).
[0122]
FIG. 4 additionally shows an example of wiring when each of the vertical charge transfer elements 20 is driven by the eight-phase vertical drive signals φV1 to φV8. FIG. 5 additionally shows an example of wiring when the horizontal charge transfer element 45 is driven by 8-phase horizontal drive signals φH1 to φH8. 4 and 5 also show wiring examples when the CCD line memory unit 40 is driven by the control signal φLM.
[0123]
As shown in FIG. 4, each of the first to second vertical transfer electrodes 31 to 32 and the first to third auxiliary transfer electrodes 33 to 35 are divided into eight groups, and the vertical drive signals φV1 to φV1 that are different for each group. φV8 is supplied. One group includes first vertical transfer electrodes 31, second vertical transfer electrodes 32, first auxiliary transfer electrodes 33, second auxiliary transfer electrodes 34, or third auxiliary transfer electrodes 35 selected every seven lines. . The control signal φLM is supplied to each of the first to second transfer control electrodes 41 to 42.
[0124]
As shown in FIG. 5, each of the horizontal charge transfer stage and the auxiliary horizontal charge transfer stage is divided into eight groups, and different horizontal drive signals φH1 to φH8 are supplied for each group. One group is constituted by horizontal charge transfer stages selected every seven.
[0125]
In the horizontal charge transfer element 45, each horizontal charge transfer stage is divided into eight groups starting from the horizontal charge transfer stage corresponding to the leftmost vertical charge transfer channel 20a in FIG. If these groups are called the first group to the eighth group in order, the horizontal drive signal φH1 is supplied to the first group, the horizontal drive signal φH2 is supplied to the second group, and so on. A horizontal drive signal φH8 is supplied to the group.
[0126]
A horizontal drive signal φH6 is supplied to the most downstream auxiliary horizontal charge transfer stage, and a horizontal drive signal φH7 is supplied to the second auxiliary horizontal charge transfer stage from the downstream. A horizontal drive signal φH8 is supplied to the most upstream auxiliary horizontal charge transfer stage (the third auxiliary horizontal charge transfer stage from the downstream).
[0127]
In the present specification, the number of horizontal transfer electrodes in the horizontal charge transfer element after being connected to a voltage supply line that supplies a drive signal is counted under the following promise.
[0128]
That is, two or three or more horizontal transfer electrodes that are adjacent to each other and connected to the same voltage supply wiring are collectively counted as one. Under this promise, the number of two horizontal transfer electrodes that are adjacent to each other but are connected to different voltage supply lines is two. Also, the number of two horizontal transfer electrodes that are connected to the same voltage supply wiring but are separated from each other is two.
[0129]
The above convention shall also apply in the following cases: That is, a plurality of first charge transfer channel regions (for example, downstream end portions in each of the plurality of vertical charge transfer channels 20a) and second charges electrically connected to each of the first charge transfer channel regions. A charge transfer device including a charge transfer element including a transfer channel (for example, a horizontal charge transfer element 45) having a plurality of transfer electrodes formed on the second charge transfer channel via an electrically insulating film. In addition, the present invention is also applied when counting the number of transfer electrodes in the charge transfer device in which each of these transfer electrodes is connected to a predetermined voltage supply wiring. It is also applied when counting the number of transfer control electrodes in the CCD line memory section.
[0130]
According to the above convention, the horizontal charge transfer element 45 shown in FIG. 5 has one horizontal transfer electrode per one horizontal charge transfer stage 45a and one auxiliary horizontal charge transfer stage 45b. The horizontal charge transfer element 45 has a plurality of groups of horizontal transfer electrodes, each group including eight horizontal transfer electrodes that are continuous in the photoelectric conversion element row direction. Each of the eight horizontal transfer electrodes constituting one group is connected to a different voltage supply line. Each of the horizontal transfer electrodes having a period of 8 is connected to the same voltage supply line.
[0131]
In the CCD imaging system 100 (see FIG. 1), drive signals φV1 to φV8 and control signals φLM and φH1 to φH8 having predetermined waveforms are supplied from the drive circuit 65 to the CCD image sensor 10 according to the imaging mode. Each of the vertical charge transfer elements 20, the CCD line memory unit 40, and the horizontal charge transfer element 45 performs a predetermined operation according to the imaging mode of the CCD imaging system 100.
[0132]
Hereinafter, an example of operations of the vertical charge transfer elements 20, the CCD line memory unit 40, and the horizontal charge transfer element 45 when the imaging mode of the CCD imaging system 100 is the monitor mode will be described.
[0133]
When the imaging mode of the CCD imaging system 100 is the monitor mode, for example, half-thinning scanning is performed. Further, vertical addition of charges is performed in each vertical charge transfer element 20, and horizontal addition of charges is performed in the horizontal charge transfer element 45.
[0134]
In the ½ thinning scanning, charges are read out to each vertical charge transfer element 20 from ½ photoelectric conversion element rows among all the photoelectric conversion element rows, for example, every other photoelectric conversion element row. For example, the readout pulse is superimposed on the vertical drive signals φV5 and φV1. A read pulse may be superimposed on the vertical drive signals φV7 and φV3.
[0135]
In order to perform vertical addition of charges in each vertical charge transfer element 20, as described below, the readout pulse is superimposed on the vertical drive signal φV5 and the vertical drive signal φV1 at different timings.
[0136]
First, the first read pulse is superimposed on the vertical drive signal φV5. As a result, charges are read out from each of the photoelectric conversion elements 15 in the fourth row adjacent to the transfer electrode 31 to which the vertical drive signal φV5 is applied, to the corresponding vertical charge transfer element 20.
[0137]
Next, these charges are transferred downstream by 4 vertical charge transfer stages (2 rows) and distributed to each of the vertical charge transfer stages to which the vertical drive signal φV1 is supplied.
[0138]
Thereafter, the second read pulse is superimposed on the vertical drive signal φV1, and the corresponding vertical charge transfer element is transferred from each of the photoelectric conversion elements 15 in the fourth row adjacent to the transfer electrode 31 to which the vertical drive signal φV1 is applied. The charge is read to 20.
[0139]
The charge read by the second read pulse is added (mixed) to the charge already read by the first read pulse in each of the vertical charge transfer stages to which the vertical drive signal φV1 is supplied.
[0140]
Each of the charges added (vertically added) in each vertical charge transfer element 20 is transferred further downstream and reaches a transfer control stage 40 a constituting the CCD line memory unit 40.
[0141]
As shown in FIG. 7, in order to perform horizontal addition of charges in the horizontal charge transfer element 45, each vertical charge transfer channel 20a is divided into two groups, for example, a first group Gp1 and a second group Gp2. Charges are transferred from the CCD line memory unit 40 to the horizontal charge transfer element 45 at different timings for each group.
[0142]
The first group Gp1 includes each of the vertical charge transfer channels 20a corresponding to the horizontal charge transfer stages to which the horizontal drive signals φH1 to φH4 are supplied. The second group Gp2 includes each of the vertical charge transfer channels 20a corresponding to the horizontal charge transfer stages to which the horizontal drive signals φH5 to φH8 are supplied. Each of the first group Gp1 and the second group Gp2 includes a predetermined number of subgroups Sg each including four vertical charge transfer channels 20a adjacent in the photoelectric conversion element row direction. FIG. 7 shows two subgroups Sg1 and Sg2 for the first group Gp1 and the second group Gp2.
[0143]
Since all the constituent elements shown in FIG. 7 are shown in FIG. 5, the same reference numerals as those used in FIG.
[0144]
Each of the subgroups Sg includes a total of four vertical charge transfer channels 20a corresponding to a total of four photoelectric conversion element arrays arranged below each of the first to fourth color filter arrays FC1 to FC4 shown in FIG. Consists of.
[0145]
Hereinafter, after transferring the charge from each of the vertical charge transfer channels 20a of the second group Gp2 to the horizontal charge transfer element 45, the charge is transferred from each of the vertical charge transfer channels 20a of the first group Gp1 to the horizontal charge transfer element 45. 8, FIG. 9A, FIG. 9B, FIG. 10A, FIG. 10B, and FIG. 11A regarding the method of performing horizontal charge addition in the horizontal charge transfer element 45. 11 (B), FIG. 12 (A), FIG. 12 (B), FIG. 13 (A), FIG. 13 (B), FIG. 14 (A), FIG. 14 (B), FIG. Explanation will be made with reference to FIG.
[0146]
In the following description, the charges transferred through the individual vertical charge transfer channels 20a are changed according to the color of the color filter arranged above the photoelectric conversion element 15 corresponding to the vertical charge transfer channel 20a. These are referred to as “charge g1”, “charge r”, “charge g2”, and “charge b”. Each of the four vertical charge transfer channels 20a constituting one subgroup Sg transfers charge g1, charge r, charge g2, and charge b sequentially from the left side in FIG.
[0147]
FIG. 8 shows an example of waveforms of the control signal φLM and the horizontal drive signals φH1 to φH8 when the charges are horizontally added in the horizontal charge transfer element 45.
[0148]
FIGS. 9A and 9B schematically show the principle of transferring charges from the CCD line memory section 40 to the horizontal charge transfer element 45.
[0149]
FIGS. 10A to 10B schematically show the state of charge distribution at times t1 to t2 shown in FIG.
[0150]
FIGS. 11A to 11B schematically show the state of charge distribution at times t3 to t4 shown in FIG.
[0151]
12A to 12B schematically show the state of charge distribution at times t5 to t6 shown in FIG.
[0152]
FIGS. 13A to 13B schematically show the state of charge distribution at times t7 to t8 shown in FIG.
[0153]
FIGS. 14A to 14B schematically show the state of charge distribution at times t9 to t10 shown in FIG.
[0154]
FIG. 15A to FIG. 15B schematically show the state of charge distribution at times t11 to t12 shown in FIG.
[0155]
Since all the components shown in FIGS. 10A to 15B are shown in FIG. 7, the same reference numerals as those used in FIG. Description is omitted.
[0156]
As shown in FIG. 8, at time t0 before transferring charges from the CCD line memory section 40 to the horizontal charge transfer element 45, the horizontal drive signals φH1 to φH4 are at a low level L (for example, 0 V), and horizontal drive is performed. Signals φH5 to φH8 and control signal φLM are at high level H (for example, +3.3 V).
[0157]
As shown in FIG. 9A, when the horizontal drive signal φHn (n represents an arbitrary integer of 1 to 8; the same applies hereinafter) is at the low level L, the signal below the first horizontal transfer electrode 47 is The potential of the horizontal charge transfer channel 46 (potential barrier region) is equal to the vertical charge transfer channel 20a under the second transfer control electrode 42 regardless of whether the control signal φLM is at the high level H or the low level L. It is lower than the potential of (second region). Therefore, when the horizontal drive signal φHn is at the low level L, the charge Q remains in the CCD line memory unit 40 without being transferred from the CCD line memory unit 40 to the horizontal charge transfer element 45.
[0158]
On the other hand, as shown in FIG. 9B, when the horizontal drive signal φHn is at the high level H, the potential of the horizontal charge transfer channel 46 (potential barrier region) under the first horizontal transfer electrode 47 is controlled by the control signal. It is lower than the potential of the vertical charge transfer channel 20a (second region) under the second transfer control electrode 42 when φLM is at the high level H. Therefore, even if the horizontal drive signal φHn is at the high level H, if the control signal φLM is at the high level H, the charge Q is not transferred from the CCD line memory unit 40 to the horizontal charge transfer element 45, and the CCD line It remains in the memory unit 40.
[0159]
Accordingly, no charge is transferred from the CCD line memory section 40 to the horizontal charge transfer element 45 at time t0 shown in FIG.
[0160]
As at time t1 shown in FIG. 8, when transferring charges from the CCD line memory section 40 to the horizontal charge transfer element 45, the control signal φLM is changed from the high level H to the low level L (eg, 0 V). The horizontal drive signals φH1 to φH4 are set to the low level L, and the horizontal drive signals φH5 to φH8 are set to the high level H.
[0161]
As shown in FIG. 9B, when the horizontal drive signal φHn is at the high level H and the control signal φLM is at the low high level L, the horizontal charge transfer channel 46 below the first horizontal transfer electrode 47. The potential of the (potential / barrier region) becomes higher than the potential of the vertical charge transfer channel 20a (second region) under the second transfer control electrode. Therefore, the charge Q is transferred from the CCD line memory unit 40 to the horizontal charge transfer element 45.
[0162]
As shown in FIG. 10A, at time t1 shown in FIG. 8, the charge is transferred from the CCD line memory unit 40 to each horizontal charge transfer stage to which the horizontal drive signals φH5 to φH8 are supplied. That is, charges g 1, r, g 2, or b are transferred from the vertical charge transfer channel 20 a of the second group Gp 2 to the horizontal charge transfer element 45. No charge is transferred from the CCD line memory unit 40 to each of the horizontal charge transfer stages to which the horizontal drive signals φH1 to φH4 are supplied. That is, no charge is transferred from each of the vertical charge transfer channels 20a of the first group Gp1 to the horizontal charge transfer element 45.
[0163]
Next, the control signal φLM changes from the low level L to the high level H, and the transfer of charges from the CCD line memory unit 40 to the horizontal charge transfer element 45 is prohibited. Thereafter, as at time t2 in FIG. 8, the horizontal drive signal φH4 is changed from the low level L to the high level H, and the horizontal drive signal φH5 is changed from the high level H to the low level L. The charges in the horizontal charge transfer stage supplied with the horizontal drive signal φH5 are transferred to the horizontal charge transfer stage supplied with the horizontal drive signal φH4. The horizontal charge transfer stage to which the horizontal drive signal φH5 is supplied becomes empty.
[0164]
FIG. 10B shows the distribution state of the charges g1, r, g2 and b at time t2 shown in FIG. From the state at time t1 shown in FIG. 10A, each of the charges g1 in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage.
[0165]
Next, as at time t3 in FIG. 8, the horizontal drive signal φH4 is changed from the high level H to the low level L, and the horizontal drive signal φH3 is changed from the low level L to the high level H. Further, the horizontal drive signal φH5 is changed from the low level L to the high level H, and the horizontal drive signal φH6 is changed from the high level H to the low level L.
[0166]
The charges in the horizontal charge transfer stage supplied with the horizontal drive signal φH4 or φH6 are transferred to the horizontal charge transfer stage supplied with the horizontal drive signal φH3 or φH5.
[0167]
As described above, the accordion transfer that is gradually transferred from the charge on the downstream side is performed in units of four charges transferred from one subgroup Sg. In this accordion transfer, the interval between the downstream charge and the most upstream charge gradually increases until a certain time. Thereafter, as will be described later, the transfer of the most downstream charge is stopped and only the upstream charge is gradually transferred to the downstream side. The interval between the most downstream charge and the upstream charge gradually decreases. The operation of expanding the charge distribution area to the downstream side and the operation of moving the upstream end of the charge distribution area to the downstream side are performed a desired number of times.
[0168]
FIG. 11A shows the distribution state of the charges g1, r, g2 and b at time t3 shown in FIG. From the state at time t2 shown in FIG. 10B, each of the charges g1 and r in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage.
[0169]
Next, as at time t4 in FIG. 8, the horizontal drive signal φH2 is set to the high level H, and the horizontal drive signal φH3 is set to the low level L. The horizontal drive signal φH4 is set to the high level H, and the horizontal drive signal φH5 is set to the low level L. Further, the horizontal drive signal φH6 is set to the high level H, and the horizontal drive signal φH7 is set to the low level L. The charges distributed in the horizontal charge transfer stages to which the horizontal drive signals φH3, φH5, and φH7 are supplied are transferred downstream by one horizontal charge transfer stage.
[0170]
FIG. 11B shows the distribution state of the charges g1, r, g2, and b at time t4 shown in FIG. From the state at time t3 shown in FIG. 11A, each of the charges g1, r, and g2 in the horizontal charge transfer element 45 is transferred to the downstream side by one horizontal charge transfer stage. Charges are distributed over the widest range, and each of the four types of charges g1, r, g2, and b is distributed in every other horizontal charge transfer stage. In this state, four types of charges can be transferred in synchronization with each other.
[0171]
Next, as at time t5 in FIG. 8, the horizontal drive signal φH1 is set to the high level H, and the horizontal drive signal φH2 is set to the low level L. The horizontal drive signal φH3 is set to the high level H, and the horizontal drive signal φH4 is set to the low level L. The horizontal drive signal φH5 is set to the high level H, and the horizontal drive signal φH6 is set to the low level L. Further, the horizontal drive signal φH7 is set to the high level H, and the horizontal drive signal φH8 is set to the low level L. The charges distributed in the horizontal charge transfer stages to which the horizontal drive signals φH2, φH4, φH6, and φH8 are supplied are transferred downstream by one horizontal charge transfer stage.
[0172]
FIG. 12A shows the distribution state of the charges g1, r, g2, and b at time t5 shown in FIG. From the state at time t4 shown in FIG. 11B, each of the charges g1, r, g2 and b in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage. Each of the charges g1 in the horizontal charge transfer element 45 is distributed to horizontal charge transfer stages corresponding to the vertical charge transfer channel 20a that transfers the charge g1 among the vertical charge transfer channels 20a included in the first group Gp1. Thereafter, in the four charge units transferred from one subgroup Sg, the upstream charge is gradually transferred to the downstream side while the transfer of the most downstream charge g1 is stopped to narrow the charge distribution width. .
[0173]
As at time t6 in FIG. 8, the horizontal drive signal φH2 is set to the high level H, and the horizontal drive signal φH3 is set to the low level L. The horizontal drive signal φH4 is set to the high level H, and the horizontal drive signal φH5 is set to the low level L. Further, the horizontal drive signal φH6 is set to the high level H, and the horizontal drive signal φH7 is set to the low level L. The charges distributed in the horizontal charge transfer stages to which the horizontal drive signals φH3, φH5, and φH7 are supplied are transferred downstream by one horizontal charge transfer stage.
[0174]
FIG. 12B shows the distribution state of the charges g1, r, g2 and b at time t6 shown in FIG. From the state at time t5 shown in FIG. 12A, each of the charges r, g2, and b in the horizontal charge transfer element 45 is transferred to the downstream side by one horizontal charge transfer stage.
[0175]
Next, as at time t7 in FIG. 8, the horizontal drive signal φH3 is set to the high level H, and the horizontal drive signal φH4 is set to the low level L. Further, the horizontal drive signal φH5 is set to the high level H, and the horizontal drive signal φH6 is set to the low level L. The charges distributed in the horizontal charge transfer stages to which the horizontal drive signals φH4 and φH6 are supplied are transferred downstream by one horizontal charge transfer stage.
[0176]
FIG. 13A shows the distribution state of the charges g1, r, g2, and b at time t7 shown in FIG. From the state at time t6 shown in FIG. 12B, each of the charges g2 and b in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage.
[0177]
Next, as at time t8 in FIG. 8, the horizontal drive signal φH4 is set to the high level H, and the horizontal drive signal φH5 is set to the low level L. Each charge distributed in the horizontal charge transfer stage to which the horizontal drive signal φH5 is supplied is transferred downstream by one horizontal charge transfer stage.
[0178]
FIG. 13B shows the distribution state of the charges g1, r, g2, and b at time t8 shown in FIG. From the state at time t7 shown in FIG. 13A, each of the charges b in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage.
[0179]
As shown in FIG. 13B, each of the charges g1, r, g2 and b in the horizontal charge transfer element 45 corresponds to a horizontal charge transfer stage corresponding to each of the vertical charge transfer channels 20a of the first group Gp1, that is, Distributed to horizontal charge transfer stages to which horizontal drive signals φH1 to φH4 are supplied. In each of the transfer control stages corresponding to the vertical charge transfer channels 20a of the first group Gp1, charges that have not yet been transferred to the horizontal charge transfer element 45 remain.
[0180]
Next, as at time t9 in FIG. 8, the control signal φLM changes from the high level H to the low level L. The horizontal drive signals φH1 to φH4 are each at a high level H, and the horizontal drive signals φH5 to φH8 are each at a low level L. Therefore, charges are transferred from the CCD line memory unit 40 to each of the horizontal charge transfer stages to which the horizontal drive signals φH1 to φH4 are supplied. That is, charges g 1, r, g 2 or b are transferred to the horizontal charge transfer element 45 from each of the vertical charge transfer channels 20 a of the first group Gp 1.
[0181]
FIG. 14A shows the distribution state of the charges g1, r, g2, and b at time t9 shown in FIG. In the horizontal charge transfer element 45, the charges g1, the charges r, the charges g2 and the charges b are added (mixed). Hereinafter, in this specification, two charges g1, 2 charges r, 2 charges g2, and 2 charges b added (mixed) to each other are referred to as "charge g1-g1" and "charge r-r", respectively. ”,“ Charge g2-g2 ”or“ charge bb ”.
[0182]
Next, the control signal φLM changes from the low level L to the high level H, and the transfer of charges from the CCD line memory unit 40 to the horizontal charge transfer element 45 is prohibited. Subsequently, as at time t10 in FIG. 8, the horizontal drive signal φH1 is set to the low level L, and the horizontal drive signal φH8 is set to the high level H. The horizontal drive signals φH2, φH3, and φH4 remain at the high level H, and the horizontal drive signals φH5, φH6, and φH7 remain at the low level L. Each charge distributed in the horizontal charge transfer stage supplied with the horizontal drive signal φH1 is transferred downstream by one horizontal charge transfer stage.
[0183]
FIG. 14B shows the distribution state of the charges g1-g1, rr, g2-g2, and bb at the time t10 shown in FIG. From the state at time t9 shown in FIG. 14A, each of the charges g1-g1 in the horizontal charge transfer element 45 is transferred to the downstream side by one horizontal charge transfer stage. The most downstream charges g1-g1 are distributed in the most upstream auxiliary horizontal charge transfer stage.
[0184]
Next, as at time t11 in FIG. 8, the horizontal drive signal φH1 is set to the high level H, and the horizontal drive signal φH2 is set to the low level L. Further, the horizontal drive signal φH7 is set to the high level H, and the horizontal drive signal φH8 is set to the low level L. The charges distributed in the auxiliary horizontal charge transfer stage or the horizontal charge transfer stage supplied with the horizontal drive signals φH2 and φH8 are transferred downstream by one auxiliary horizontal charge transfer stage or one horizontal charge transfer stage, respectively. The
[0185]
FIG. 15A shows the distribution state of the charges g1-g1, rr, g2-g2, and b-b at the time t11 shown in FIG. From the state at time t10 shown in FIG. 14B, each of the charges g1-g1 and rr in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage.
[0186]
Next, as at time t12 in FIG. 8, the horizontal drive signal φH2 is set to the high level H, and the horizontal drive signal φH3 is set to the low level L. The horizontal drive signal φH6 is set to the high level H, and the horizontal drive signal φH7 is set to the low level L. Further, the horizontal drive signal φH8 is set to the high level H, and the horizontal drive signal φH1 is set to the low level L. The charges distributed in the auxiliary horizontal charge transfer stage or the horizontal charge transfer stage to which the horizontal drive signals φH1, φH3, and φH7 are supplied are respectively downstream by one auxiliary horizontal charge transfer stage or one horizontal charge transfer stage. Transferred. The accordion transfer ends.
[0187]
FIG. 15B shows the distribution state of the charges g1-g1, rr, g2-g2, and bb at the time t12 shown in FIG. From the state at time t10 shown in FIG. 14B, each of the charges g1-g1 in the horizontal charge transfer element 45 is transferred downstream by one auxiliary horizontal charge transfer stage or one horizontal charge transfer stage, Each of the charges rr is transferred downstream by one auxiliary horizontal charge transfer stage or one horizontal charge transfer stage, and each of charges g2-g2 is transferred downstream by one horizontal charge transfer stage.
[0188]
As a result, in the horizontal charge transfer element 45, the charges g1-g1, rr, and g2 are provided every one auxiliary horizontal charge transfer stage or every other horizontal charge transfer stage from the most downstream auxiliary horizontal charge transfer stage to the upstream. -G2 and bb are repeatedly distributed in this order.
[0189]
Thereafter, the horizontal drive signals φH1, φH3, φH5, and φH7 are combined to change the level repeatedly from the low level L to the high level H and from the high level H to the low level L under the same phase. . Further, the horizontal drive signals φH2, φH4, φH6 and φH8 are combined to change the level repeatedly from the high level H to the low level L and from the low level L to the high level H under the same phase. At this time, the phases of the horizontal drive signals φH1, φH3, φH5, and φH7 are opposite to the phases of the horizontal drive signals φH2, φH4, φH6, and φH8.
[0190]
As a result, each of the charges g1-g1, rr, g2-g2, and bb in the horizontal charge transfer element 45 is transferred toward the output unit 60 in synchronization with each other.
[0191]
By controlling the line memory unit 40 and the horizontal charge transfer element 45 as described above, desired charges can be added (horizontal addition) in the horizontal charge transfer element 45.
[0192]
The output unit 60 sequentially outputs image signals (signal voltages) based on the charges received from the horizontal charge transfer element 45. The video signal processing circuit 70 shown in FIG. 1 generates image data using these image signals (signal voltages). The image data generated by the video signal processing circuit 70 is sent to the image data output unit 75 and temporarily stored in a storage medium such as a frame memory. Thereafter, image data is supplied from the image data output unit 75 to the display unit 80, and the display unit 80 displays an image.
[0193]
The CCD imaging system 100 including the CCD image sensor 10a according to the first embodiment can perform monitor display by performing vertical and horizontal charge addition as described above. A moving image can be displayed on a monitor, and a still image can be displayed on a monitor. It is also possible to perform only horizontal charge addition.
[0194]
Since the image data is obtained by vertically and horizontally adding the charges, it becomes easier to obtain a better reproduced image as compared with the case where the image data is obtained by performing only the vertical addition of the charges.
[0195]
Further, since the number of horizontal charge transfer stages in the horizontal charge transfer element 45 is one for one vertical charge transfer channel, the following advantages are obtained.
[0196]
That is, the length of one horizontal reading period under the same data rate is almost halved as compared with a conventional horizontal charge transfer device in which two horizontal charge transfer stages are provided for one vertical charge transfer channel. Shortened. Along with this, the number of frames for monitor display can be increased approximately twice, and it becomes easy to perform more natural monitor display. When monitor display is performed with the same number of frames as in the prior art, the data rate is approximately halved, so that the driving frequency of the horizontal charge transfer element can be reduced to approximately ½. As a result, the driving power of the horizontal charge transfer element, which is a main power consumption source in the CCD image pickup system, can be reduced to almost half.
[0197]
On the other hand, when the imaging mode of the CCD imaging system 100 is the still image recording mode, each vertical charge transfer element 20 is driven under, for example, interlace scanning. Each of the charges read from one photoelectric conversion element row to each vertical charge transfer element 20 is transferred to the CCD line memory unit 40 at the same timing. There is no vertical charge addition.
[0198]
Also in the still image recording mode, the vertical charge transfer channels 20a are divided into, for example, two groups. Charges are transferred from the CCD line memory unit 40 to the horizontal charge transfer element 45 at different timings for each group.
[0199]
For example, when each vertical charge transfer channel 20a is divided into two groups, one group is constituted by the vertical charge transfer channels 20a corresponding to even columns when the photoelectric conversion element columns are divided into even columns and odd columns. Is done. The other group is constituted by the vertical charge transfer channels 20a corresponding to the odd columns.
[0200]
First, charges are transferred from the vertical charge transfer channels 20 a of one group to the horizontal charge transfer element 45. After these charges have been transferred from the horizontal charge transfer element 45 to the output unit 60, the charges are transferred from the vertical charge transfer channels 20a of the other group to the horizontal charge transfer element 45, and further transferred to the output unit 60. The
[0201]
Charge transfer from the CCD line memory section 40 to the horizontal charge transfer element 45 is performed according to the principle already described with reference to FIG.
[0202]
At the time of charge transfer in the horizontal charge transfer element 45, the horizontal drive signals φH1, φH3, φH5 and φH7 are combined to change from the low level L to the high level H under the same phase, and from the high level H The level is repeatedly changed from low to low. Further, the horizontal drive signals φH2, φH4, φH6 and φH8 are combined to change the level repeatedly from the high level H to the low level L and from the low level L to the high level H under the same phase. At this time, the phases of the horizontal drive signals φH1, φH3, φH5, and φH7 are opposite to the phases of the horizontal drive signals φH2, φH4, φH6, and φH8.
[0203]
As a result, the charges in the horizontal charge transfer element 45 are transferred toward the output unit 60 in synchronization with each other.
[0204]
The output unit 60 sequentially outputs image signals (signal voltages) based on the charges received from the horizontal charge transfer element 45. The video signal processing circuit 70 shown in FIG. 1 generates still image data using these image signals (signal voltages). The image data generated by the video signal processing circuit 70 is sent to the image data output unit 75 and temporarily stored in a storage medium such as a frame memory.
[0205]
Thereafter, image data is supplied from the image data output unit 75 to the display unit 80, and the display unit 80 displays a still image. Alternatively, image data is supplied from the image data output unit 75 to the recording unit 82 and still image data is recorded on a recording medium such as a memory card. The CCD imaging system 100 generates still image data based on the charges accumulated in all the photoelectric conversion elements 15. Of course, it is also possible to perform vertical or horizontal charge addition in the still image recording mode.
[0206]
When the waveforms of the control signal φLM and the horizontal drive signals φH1 to φH8 are the waveforms shown in FIG. 8, the charges g1, the charges r, the charges g2, and the charges b are included in the horizontal charge transfer element 45 as described above. Added (mixed).
[0207]
By selecting the waveforms of the control signal φLM and the horizontal drive signals φH1 to φH8, as described below, the charges r and charges b are added (mixed) in the horizontal charge transfer element 45, and further, the charges g1 and The charge g2 can be added (mixed).
[0208]
FIG. 16 shows a control signal φLM and a horizontal drive signal that can add (mix) the charges g1 and g2 in the horizontal charge transfer element 45 and further add (mix) the charges r and b. An example of the waveform of φH1 to φH8 is shown.
[0209]
FIG. 17 shows the grouping specifications for each vertical charge transfer channel 20a.
[0210]
18A and 18B schematically show the state of charge distribution at times T1 and T2 shown in FIG.
[0211]
FIGS. 19A and 19B schematically show the state of charge distribution at times T3 and T5 shown in FIG.
[0212]
20A and 20B schematically show the state of charge distribution at times T7 and T10 shown in FIG.
[0213]
17 to 20B are all shown in FIG. 5, the same reference numerals as those used in FIG. 5 are assigned to the respective constituent elements, and the description thereof is omitted. To do.
[0214]
As shown in FIG. 17, by making the waveforms of the horizontal drive signals φH1 to φH8 into the waveforms shown in FIG. 16, each vertical charge transfer channel 20a is divided into two groups, a first group Gp1 and a second group Gp2. . Charges are transferred from the CCD line memory section 40 to the horizontal charge transfer element 45 at different timings for these two groups.
[0215]
Each of the first group Gp1 and the second group Gp2 includes a predetermined number of subgroups Sg including four vertical charge transfer channels 20a selected in a predetermined pattern in the photoelectric conversion element row direction. FIG. 17 shows three subgroups Sg1, Sg2, and Sg3 included in the first group Gp1, and two subgroups Sg1 and g2 included in the second group Gp2.
[0216]
Each of the subgroups Sg in the first group Gp1 has a vertical charge transfer channel 20a corresponding to the first (1 + 8y) (y represents an integer of 0 or more; the same shall apply hereinafter) counting from the left in FIG. Each of the vertical charge transfer channels 20a corresponding to the first, third, and fourth counts from the transfer channel 20a to the right side. These vertical charge transfer channels 20a transfer charge g1, charge r, charge b, and charge g1 in order from the left.
[0217]
Each of the subgroups Sg in the second group Gp2 includes the (3 + 8y) th vertical charge transfer channel 20a counted from the left in FIG. 17, and the third, fourth, and fifthth counted from the vertical charge transfer channel 20a to the right. Each vertical charge transfer channel 20a. These vertical charge transfer channels 20a transfer charge g2, charge r, charge g2, and charge b in order from the left.
[0218]
Hereinafter, after transferring the charge from each of the vertical charge transfer channels 20a of the second group Gp2 to the horizontal charge transfer element 45, the charge is transferred from each of the vertical charge transfer channels 20a of the first group Gp1 to the horizontal charge transfer element 45. A method of performing horizontal charge addition in the horizontal charge transfer element 45 will be specifically described.
[0219]
As shown in FIG. 16, at a time T0 before transferring charges from the CCD line memory unit 40 to the horizontal charge transfer element 45, the horizontal drive signals φH1, φH2, φH4, and φH5 are at a low level L (eg, 0 V). Yes, the horizontal drive signals φH3, φH6, φH7, φH8 and the control signal φLM are at a high level H (for example, +3.3 V). Therefore, no charge is transferred from the CCD line memory section 40 to the horizontal charge transfer element 45 at time T0 shown in FIG.
[0220]
As shown at time T1 in FIG. 16, when transferring charges from the CCD line memory section 40 to the horizontal charge transfer element 45, the control signal φLM is set to the low level L, and the horizontal drive signals φH3 and φH6 to φH8 are respectively set. Set to high level H. Horizontal drive signals φH1 to φH2 and φH4 to φH5 are set to low level L, respectively.
[0221]
As shown in FIG. 18A, at time T1 shown in FIG. 16, charges are transferred from the CCD line memory unit 40 to each horizontal charge transfer stage to which the horizontal drive signals φH3 and φH6 to φH8 are supplied. . That is, the charges g2, g1, or b are transferred to the horizontal charge transfer element 45 from each of the vertical charge transfer channels 20a of the second group Gp2. No charge is transferred from each of the vertical charge transfer channels 20a of the first group Gp1 to the horizontal charge transfer element 45.
[0222]
Next, the control signal φLM is changed from the low level L to the high level H, and the transfer of charges from the CCD line memory unit 40 to the horizontal charge transfer element 45 is prohibited. Thereafter, as at time T2 in FIG. 16, the horizontal drive signal φH5 is set to the high level H, and the horizontal drive signal φH6 is set to the low level L. The charges in the horizontal charge transfer stage supplied with the horizontal drive signal φH6 are transferred to the horizontal charge transfer stage supplied with the horizontal drive signal φH5. At this time, the horizontal drive signal φH1 may be changed from the low level L to the high level H as shown by hatching in FIG.
[0223]
FIG. 18B shows the distribution state of the charges g1, r, g2, and b at time T2 shown in FIG. From the state at time T1 shown in FIG. 18A, each of the charges r in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage.
[0224]
Next, as at time T3 in FIG. 16, the horizontal drive signal φH2 is set to the high level H, and the horizontal drive signal φH3 is set to the low level L. The horizontal drive signal φH4 is set to the high level H, and the horizontal drive signal φH5 is set to the low level L. Further, the horizontal drive signal φH6 is set to the high level H, and the horizontal drive signal φH7 is set to the low level L. The charges in the horizontal charge transfer stage to which the horizontal drive signals φH3, φH5, and φH7 are supplied are transferred downstream by one horizontal charge transfer stage.
[0225]
FIG. 19A shows the distribution state of the charges g1, r, g2 and b at time T3 shown in FIG. From the state at time T2 shown in FIG. 18B, the charges g2 and r in the horizontal charge transfer element 45 are transferred downstream by one horizontal charge transfer stage.
[0226]
Next, as at time T4 in FIG. 16, the horizontal drive signal φH1 is set to the high level H, and the horizontal drive signal φH2 is set to the low level L. The horizontal drive signal φH3 is set to the high level H, and the horizontal drive signal φH4 is set to the low level L. The horizontal drive signal φH5 is set to the high level H, and the horizontal drive signal φH6 is set to the low level L. Further, the horizontal drive signal φH7 is set to the high level H, and the horizontal drive signal φH8 is set to the low level L. The charges in the horizontal charge transfer stage to which the horizontal drive signals φH2, φH4, φH6, and φH8 are supplied are transferred downstream by one horizontal charge transfer stage.
[0227]
As a result, each of the charges g2 in the horizontal charge transfer element 45 is distributed to horizontal charge transfer stages corresponding to each of the vertical charge transfer channels 20a that transfer the charge g1 among the vertical charge transfer channels 20a of the first group Gp1. To do. In each of the transfer control stages corresponding to the vertical charge transfer channels 20a of the first group Gp1, charges that have not yet been transferred to the horizontal charge transfer element 45 remain.
[0228]
Next, the control signal φLM is changed from the high level H to the low level L as at time T5 in FIG. Horizontal drive signals φH1 and φH5 are at high level H, and horizontal drive signals φH2 to φH4 and φH6 to φH8 are at low level L. Therefore, charges are transferred from the CCD line memory unit 40 to each of the horizontal charge transfer stages to which the horizontal drive signals φH1 and φH5 are supplied.
[0229]
FIG. 19B shows the distribution state of the charges g1, r, g2 and b at time T5 shown in FIG. The charge g1 is supplied from each of the vertical charge transfer channels 20a for transferring the charge g1 among the vertical charge transfer channels 20a included in the first group Gp1 to each of the horizontal charge transfer stages to which the horizontal drive signals φH1 and φH5 are supplied. Is transferred. As a result, in the horizontal charge transfer element 45, the charge g1 and the charge g2 are added (mixed). Hereinafter, in this specification, the charge r1 and the charge r2 added (mixed) to each other are referred to as “charge r1-r2”.
[0230]
Next, the control signal φLM is changed from the low level L to the high level H, and the transfer of charges from the CCD line memory unit 40 to the horizontal charge transfer element 45 is prohibited. Thereafter, as at time T6 in FIG. 16, the horizontal drive signal φH2 is set to the high level H, and the horizontal drive signal φH3 is set to the low level L. The horizontal drive signal φH4 is set to the high level H, and the horizontal drive signal φH5 is set to the low level L. The horizontal drive signal φH6 is set to the high level H, and the horizontal drive signal φH7 is set to the low level L. The horizontal drive signal φH8 is set to the high level H, and the horizontal drive signal φH1 is set to the low level L.
[0231]
The charges in the horizontal charge transfer stage to which the horizontal drive signals φH1, φH3, φH5, and φH7 are supplied are transferred downstream by one horizontal charge transfer stage. The most downstream charge r1-r2 reaches the most upstream auxiliary horizontal charge transfer stage.
[0232]
As a result, each of the charges r in the horizontal charge transfer element 45 is distributed to the horizontal charge transfer stages corresponding to the vertical charge transfer channels 20a that transfer the charge r among the vertical charge transfer channels 20a of the first group Gp1. To do.
[0233]
Next, as at time T7 in FIG. 16, the control signal φLM is changed from the high level H to the low level L. The horizontal drive signal φH2 is at the high level H, and the horizontal drive signals φH1, φH3 to φH8 are at the low level L. Therefore, charges are transferred from the CCD line memory unit 40 to each of the horizontal charge transfer stages to which the horizontal drive signal φH2 is supplied.
[0234]
FIG. 20A shows the distribution state of the charges g1, r, g2, and b at time T7 shown in FIG. The charge r is transferred from each of the vertical charge transfer channels 20a for transferring the charge r among the vertical charge transfer channels 20a included in the first group Gp1 to each of the horizontal charge transfer stages to which the horizontal drive signal φH2 is supplied. Is done.
[0235]
As a result, the two charges r are added (mixed) in the horizontal charge transfer element 45. One charge r has been transferred to the horizontal charge transfer element 45 via the vertical charge transfer channel 20a included in the second group Gp2, and the other charge r is the vertical charge included in the first group Gp1. It has been transferred to the horizontal charge transfer element 45 via the transfer channel 20a.
[0236]
Next, the control signal φLM is changed from the low level L to the high level H, and the transfer of charges from the CCD line memory unit 40 to the horizontal charge transfer element 45 is prohibited. Thereafter, as at time T8 in FIG. 16, the horizontal drive signal φH1 is set to the high level H, and the horizontal drive signal φH2 is set to the low level L. The horizontal drive signals φH3, φH5, and φH7 are set to the high level H. The horizontal drive signals φH4, φH4, φH6, and φH8 are at the low level L.
[0237]
Each of the charges distributed in the horizontal charge transfer stage or auxiliary horizontal charge transfer stage to which the horizontal drive signals φH2, φH4, φH6, φH8 are supplied corresponds to one horizontal charge transfer stage or one auxiliary horizontal charge transfer stage, respectively. Transferred downstream. That is, each of the charges g1-g2, rr, and b in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage or one auxiliary horizontal charge transfer stage.
[0238]
Next, as at time T9 in FIG. 16, the horizontal drive signal φH2 is set to the high level H, and the horizontal drive signal φH3 is set to the low level L. The horizontal drive signal φH4 is set to the high level H, and the horizontal drive signal φH5 is set to the low level L. The horizontal drive signal φH6 is set to the high level H, and the horizontal drive signal φH7 is set to the low level L. Further, the horizontal drive signal φH8 is set to the high level H, and the horizontal drive signal φH1 is set to the low level L.
[0239]
The charges distributed in the horizontal charge transfer stage or the auxiliary horizontal charge transfer stage to which the horizontal drive signals φH1, φH3, φH5, and φH7 are supplied respectively correspond to one horizontal charge transfer stage or one auxiliary horizontal charge transfer stage, Transferred downstream. That is, each of the charges g1-g2, rr, and b in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage or one auxiliary horizontal charge transfer stage.
[0240]
As a result, each of the charges b in the horizontal charge transfer element 45 is distributed to the horizontal charge transfer stages corresponding to each of the vertical charge transfer channels 20a that transfer the charge b among the vertical charge transfer channels 20a of the first group Gp1. To do.
[0241]
Next, as at time T10 in FIG. 16, the control signal φLM is changed from the high level H to the low level L. The horizontal drive signal φH4 is at the high level H, and the horizontal drive signals φH1 to φH3 and φH5 to φH8 are at the low level L. Therefore, charges are transferred from the CCD line memory unit 40 to each of the horizontal charge transfer stages to which the horizontal drive signal φH4 is supplied.
[0242]
FIG. 20B shows the distribution state of the charges g1, r, g2, and b at time T10 shown in FIG. The charge b is transferred from each of the vertical charge transfer channels 20a that transfer the charge b among the vertical charge transfer channels 20a included in the first group Gp1 to each of the horizontal charge transfer stages to which the horizontal drive signal φH4 is supplied. Is done.
[0243]
As a result, the two charges b are added (mixed) in the horizontal charge transfer element 45. One charge b has been transferred to the horizontal charge transfer element 45 via the vertical charge transfer channel 20a included in the second group Gp2, and the other charge b is the vertical charge included in the first group Gp1. It has been transferred to the horizontal charge transfer element 45 via the transfer channel 20a.
[0244]
In the horizontal charge transfer element 45, the charges g1-g2, rr, g1-g2 and the auxiliary horizontal charge transfer stage or every other horizontal charge transfer stage from the most downstream auxiliary horizontal charge transfer stage upstream. bb is repeatedly distributed in this order.
[0245]
Thereafter, as shown in FIG. 16, horizontal drive signals φH1, φH3, φH5, and φH7 are set as one set, and from the low level L to the high level H and from the high level H to the low level L under the same phase. And repeatedly change its level. Further, a set of horizontal drive signals φH2, φH4, φH6, and φH8 is set, and the level is repeatedly changed from the high level H to the low level L and from the low level L to the high level H under the same phase. At this time, the phases of the horizontal drive signals φH1, φH3, φH5 and φH7 are reversed from the phases of the horizontal drive signals φH2, φH4, φH6 and φH8.
[0246]
As a result, each of the charges g1-g1, rr, g2-g2, and bb in the horizontal charge transfer element 45 is transferred toward the output unit 60 in synchronization with each other.
[0247]
By controlling the line memory unit 40 and the horizontal charge transfer element 45 in this manner, the charges g1 and g2 are added (horizontal addition) in the horizontal charge transfer element 45, and further, the charges r and b Can be added (horizontal addition). When such horizontal addition is performed, advantages similar to those obtained when the charges are horizontally added according to the timing chart shown in FIG. 8 are obtained, and the following advantages (1) to (3) are obtained. It is done.
(1) Since the same type of charge closest in the photoelectric conversion element row direction is horizontally added, the MTF (modulation transfer function: modulation degree) in the photoelectric conversion element row direction is reduced by the addition (averaging). Can be minimized.
[0248]
That is, it is possible to minimize the decrease in the resolution of the image displayed on the monitor due to the horizontal addition.
[0249]
As described in the description of the color filter array 55 shown in FIG. 3, the green filter G1 constituting the first color filter row FC1 and the green filter G2 constituting the third color filter row FC3 are as follows. The reference numerals are merely changed for convenience, and both are made of the same material. Therefore, the charge g1 and the charge g2 are the same kind of charges.
(2) As a result of obtaining the advantage of the above (1), it becomes easy to display a high-quality reproduced image.
(3) As is clear from FIG. 16, the horizontal drive signal φH3 and the horizontal drive signal φH7 can have the same waveform. In addition, if a hatched pulse in FIG. 16 is added to the horizontal drive signal φH1, the horizontal drive signal φH1 and the horizontal drive signal φH5 can have the same waveform. Therefore, the number of types of horizontal drive signals necessary for driving the horizontal charge transfer element 45 can be reduced from 8 to 6-7.
[0250]
Accordingly, the number of voltage supply lines (horizontal drive signal supply lines) necessary for driving the horizontal charge transfer element 45 can be reduced to 6-7.
[0251]
As a result, the semiconductor chip required for manufacturing the CCD image sensor 10a can be reduced in size, and the configuration of the drive circuit 65 (see FIG. 1) can be simplified.
[0252]
Next, a CCD image sensor according to a second embodiment of the CCD image sensor 10 shown in FIG. 1 will be described.
[0253]
FIG. 21 is a partial plan view schematically showing a planar arrangement of the photoelectric conversion element, the vertical charge transfer element, the CCD line memory unit, the horizontal charge transfer element, and the output unit in the CCD image sensor 10b according to the second embodiment.
[0254]
As shown in FIG. 21, in the CCD image sensor 10b, a large number of photoelectric conversion elements 15 are arranged with a pixel shift. In this respect, the CCD image sensor 10b is greatly different from the CCD image sensor 10a according to the first embodiment.
[0255]
In addition, the CCD image sensor 10b is different from the CCD image sensor 10a in the following points (1) to (7).
(1) The shape of each photoelectric conversion element 15 in plan view and the shape of each photoelectric conversion element region 16 in plan view are octagons.
(2) Each vertical charge transfer channel 20a includes a region meandering along a corresponding photoelectric conversion element array. Accordingly, each vertical charge transfer element 20 also includes a meandering region along the corresponding photoelectric conversion element array.
(3) One read gate channel region is arranged along the lower right side of the individual photoelectric conversion element 15 in plan view.
(4) Except for the most downstream first vertical transfer electrode 31a, each of the first vertical transfer electrodes 31a has an even-numbered photoelectric conversion element row counted from the horizontal charge transfer element 45 side and an odd-numbered photoelectric photoelectric immediately downstream thereof. A region meandering along the photoelectric conversion element rows between the conversion element rows is included. The most downstream first vertical transfer electrode 31a includes a region that meanders along the photoelectric conversion element row on the downstream side of the first photoelectric conversion element row as counted from the horizontal charge transfer element 45 side.
(5) Except for the most upstream second vertical transfer electrode 32a, each of the second vertical transfer electrodes 32a has an odd-numbered photoelectric conversion element row counted from the horizontal charge transfer element 45 side and an even-numbered photoelectric immediately downstream thereof. A region meandering along the photoelectric conversion element rows between the conversion element rows is included. The most upstream second vertical transfer electrode 32a includes a region that meanders along the photoelectric conversion element row on the upstream side of the most upstream photoelectric conversion element row.
(6) Each first vertical transfer electrode 31a constitutes all the read gates 21 corresponding to the photoelectric conversion elements in the odd-numbered rows to which the first vertical transfer electrode 31a corresponds, and each second vertical transfer electrode 31a The transfer electrode 32a constitutes all the read gates 21 corresponding to the photoelectric conversion elements in the odd-numbered rows to which the second vertical transfer electrode 32a corresponds.
(7) The first auxiliary transfer electrode 33 extends in the photoelectric conversion element row direction as a whole while meandering.
[0256]
Except for these differences, the CCD image sensor 10b shown in FIG. 21 has the same configuration as the CCD image sensor 10a according to the first embodiment.
[0257]
For this reason, among the constituent elements shown in FIG. 21, those that are functionally common to the constituent elements shown in FIG. 4 are given the same reference numerals as those used in FIG. 4 and description thereof is omitted. However, the first vertical transfer electrode is given a new reference symbol “31a”, and the second vertical transfer electrode is given a new reference symbol “32a”.
[0258]
In FIG. 21, the illustration of the light shielding film, the protective film, the first planarizing film, the second planarizing film, and the microlens array is omitted. Further, although the illustration of the color filter array itself is omitted, the color of the color filter disposed on each photoelectric conversion element 15 is indicated by the symbols G1, G2, R, or B. The meanings of the symbols G1, G2, R, and B will be described later with reference to FIG.
[0259]
“Pixel shift arrangement” which is one of the features of the CCD image sensor 10b according to the present embodiment means the following arrangement in this specification.
[0260]
That is, for each photoelectric conversion element in the odd-numbered photoelectric conversion element array, each photoelectric conversion element in the even-numbered photoelectric conversion element array is approximately 1/2 the pitch of the photoelectric conversion elements in the photoelectric conversion element array, For each photoelectric conversion element in the photoelectric conversion element row corresponding to the odd-numbered photoelectric conversion element row, each of the photoelectric conversion elements in the even-numbered photoelectric conversion element row is approximately 1 / of the pitch of the photoelectric conversion elements in the photoelectric conversion element row. 2. It means an arrangement of a large number of photoelectric conversion elements that are shifted in the row direction and each of the photoelectric conversion element columns includes only odd-numbered or even-numbered photoelectric conversion elements. “Pixel shifting arrangement” is one form of a large number of photoelectric conversion elements formed in a matrix over a plurality of rows and columns.
[0261]
The above-mentioned “about 1/2 of the pitch of the photoelectric conversion elements in the photoelectric conversion element array” includes 1/2, as well as factors such as manufacturing errors, pixel position rounding errors that occur in design or mask manufacturing, and the like. Although it is deviated from 1/2, it includes values that can be regarded as substantially equivalent to 1/2 in terms of the performance of the obtained CCD image sensor and the image quality of the image. The same applies to the above-mentioned “about 1/2 of the pitch of the photoelectric conversion elements in the photoelectric conversion element row”.
[0262]
FIG. 22 is a plan view showing a part of the color filter array 55a provided in the CCD image sensor 10b. In the figure, for convenience, a red filter is indicated by a symbol R, a green filter is indicated by a symbol G1 or G2, and a blue filter is indicated by a symbol B.
[0263]
The color filter array 55a shown in FIG. 22 includes a first color filter row FC11 configured by only the green filter G1, a second color filter row FC12 in which red filters R and blue filters B are alternately arranged, and a green color. A third color filter row FC13 constituted by only the filter G2 and a fourth color filter row FC14 in which the blue filter B and the red filter R are alternately arranged are repeated in this order from the left to the right of the drawing. Has been placed. The arrangement of the red filter R and the blue filter B in the second color filter array FC12 is opposite to the arrangement of the red filter R and the blue filter B in the fourth color filter array FC14.
[0264]
Each of the color filters G1, R, G2, and B is shifted in the color filter column direction and the color filter row direction in the same manner as the photoelectric conversion elements arranged in a shifted manner.
[0265]
Each of the color filters G1, R, G2, and B has a rhombus having a diagonal line extending in the color filter column direction and a diagonal line extending in the color filter row direction in plan view. The color filter column direction is parallel to the photoelectric conversion element column direction, and the color filter row direction is parallel to the photoelectric conversion element row direction.
[0266]
The green color filter G1 constituting the first color filter row FC11 and the green color filter G2 constituting the third color filter row FC13 are simply made by changing reference numerals for convenience, and both are formed of the same material. ing.
[0267]
In the CCD image sensor 10b having the above-described configuration, for example, by driving each vertical charge transfer element 20 by the 8-phase vertical drive signals φV1 to φV8, the vertical addition of charges can be performed under 1/2 thinning scanning. Is possible. The wiring at this time is the same as the wiring example in the CCD image sensor 10a shown in FIG. 4, for example. This wiring is also shown in FIG. FIG. 21 also shows wiring for supplying the control signal φLM to the CCD line memory unit 40.
[0268]
When vertical charge addition is performed under half-thinning scanning, for example, the first read pulse is superimposed on the vertical drive signals φV5 and φV4, and the second read pulse is superimposed on the vertical drive signals φV1 and φV8. Is done.
[0269]
First, the first read pulse is supplied, and the photoelectric conversion elements 15 in the respective photoelectric conversion element rows corresponding to the (5 + 4y) th and (6 + 4y) th counted from the horizontal charge transfer element 45 side in FIG. Charge is read from each to the corresponding vertical charge transfer element 20.
[0270]
These charges are then transferred downstream by four vertical charge transfer stages. As a result, each of the vertical charge transfer elements 20 corresponding to the photoelectric conversion element columns corresponding to the odd-numbered columns counted from the left in FIG. 21 includes the first vertical transfer electrode 31a to which the vertical drive signal φV1 is supplied. Charge is distributed to each of the vertical charge transfer stages. On the other hand, each of the vertical charge transfer elements 20 corresponding to the photoelectric conversion element columns corresponding to the even columns counted from the left in FIG. 21 includes the first vertical transfer electrode 32a to which the vertical drive signal φV8 is supplied. Charge is distributed to each of the vertical charge transfer stages.
[0271]
Thereafter, the second read pulse is supplied, and the photoelectric conversion elements 15 in the respective photoelectric conversion element rows corresponding to the (1 + 4y) th and (2 + 4y) th counted from the horizontal charge transfer element 45 side in FIG. The charge is read out from each of them to the corresponding vertical charge transfer element 20.
[0272]
The charges read out by the second readout pulse are supplied with the vertical drive signal φV1 in each of the vertical charge transfer elements 20 corresponding to the photoelectric conversion element columns corresponding to the odd-numbered columns counted from the left in FIG. Charges are distributed to each of the vertical charge transfer stages configured to include one vertical transfer electrode 31a. On the other hand, each of the vertical charge transfer elements 20 corresponding to the photoelectric conversion element columns corresponding to the even columns counted from the left in FIG. 21 includes the first vertical transfer electrode 32a to which the vertical drive signal φV8 is supplied. Charge is distributed to each of the vertical charge transfer stages. In these vertical charge transfer stages, as described above, the charges read by the first read pulse are already distributed. Accordingly, in each of these vertical charge transfer stages, two charges are added (mixed).
[0273]
Each of the charges added (vertically added) in each vertical charge transfer element 20 is transferred further downstream and reaches a transfer control stage 40 a constituting the CCD line memory unit 40. At this time, all kinds of charges, that is, charge g1, charge r, charge g2, and charge are repeatedly distributed in this order from the leftmost transfer control stage 40a in FIG.
[0274]
Therefore, after that, the CCD line memory unit 40 and the horizontal charge transfer element 45 are driven in the same manner as in the case of the horizontal addition of charges in the CCD image sensor 10a according to the first embodiment. can do.
[0275]
As a result, the CCD imaging system 100 including the CCD image sensor 10b according to the second embodiment also has the same advantages as those already described for the CCD imaging system 100 including the CCD image sensor 10a according to the first embodiment. can get.
[0276]
On the other hand, when the imaging mode of the CCD imaging system 100 is the still image recording mode, for example, one frame is classified into two fields. The first field is adjacent to, for example, a photoelectric conversion element row adjacent to the upstream side of the vertical transfer electrode 31a to which the vertical drive signal φV1 is supplied and an upstream side of the vertical transfer electrode 32a to which the vertical drive signal φV8 is supplied. Photoelectric conversion element row, photoelectric conversion element row adjacent to the upstream side of the vertical transfer electrode 31a supplied with the vertical drive signal φV5, and photoelectric conversion adjacent to the upstream side of the vertical transfer electrode 32a supplied with the vertical drive signal φV4 And element rows. The second field is a photoelectric conversion element row adjacent to the upstream side of the vertical transfer electrode 31a to which the vertical drive signal φV7 is supplied and a photoelectric conversion adjacent to the upstream side of the vertical transfer electrode 32a to which the vertical drive signal φV6 is supplied. An element row, a photoelectric conversion element row adjacent to the upstream side of the vertical transfer electrode 31a to which the vertical drive signal φV3 is supplied, and a photoelectric conversion element row adjacent to the upstream side of the vertical transfer electrode 32a to which the vertical drive signal φV2 is supplied. It is comprised by.
[0277]
When reading charges from each of the photoelectric conversion elements constituting the first field to each vertical charge transfer path 20, the read pulses are superimposed on the vertical drive signals φV1, φV8, φV5, and φV4 at substantially the same timing. When reading out charges from each of the photoelectric conversion elements constituting the second field to each vertical charge transfer path 20, read pulses are superimposed on the vertical drive signals φV7, φV6, φV3, and φV2 at substantially the same timing.
[0278]
The reading of charges from the photoelectric conversion element 15 and the transfer thereof are performed in field units. Each of the charges read from the two adjacent photoelectric conversion element rows to the corresponding vertical charge transfer path 20 is transferred to the CCD line memory unit 40 at the same timing.
[0279]
Similar to the operation in the still image recording mode in the CCD image pickup system using the CCD image sensor 10a according to the first embodiment, the vertical charge transfer channels 20a are divided into, for example, two groups. Charges are transferred from the CCD line memory unit 40 to the horizontal charge transfer element 45 at different timings for each group. After the horizontal charge transfer element 45 finishes transferring each of the charges received from one group to the output unit 60, the charge is transferred from the other group to the horizontal charge transfer element 45.
[0280]
Next, a CCD image sensor according to a third embodiment of the CCD image sensor 10 shown in FIG. 1 will be described.
[0281]
FIG. 23A is a schematic diagram of a CCD image sensor 10c according to the third embodiment.
[0282]
The CCD image sensor 10c is different from the CCD image sensor 10a shown in FIG. 4 in the following points (1) to (2).
(1) The arrangement pattern of the color filters in the color filter array is a so-called G stripe RB checkered pattern. In the G-striped RB checkered color filter array, a color filter array composed of only green filters and a color filter array in which red and blue color filters are alternately and repeatedly arranged are alternately arranged. Yes.
(2) The horizontal charge transfer element 45 is driven by horizontal drive signals φH1 to φH4. Individual horizontal drive signals are supplied to every third horizontal charge transfer stage selected. Each of the first, second, third, and fourth vertical charge transfer channels 20a counted from the left in FIG. 23A is supplied with horizontal drive signals φH1, φH2, φH3, and φH4, respectively. Each auxiliary horizontal charge transfer stage receives supply of horizontal drive signals φH2, φH3, and φH4 in order from the left one in FIG.
[0283]
Except for the differences (1) to (2), the CCD image sensor 10c has the same configuration as the CCD image sensor 10a shown in FIG. Therefore, in FIG. 23A, only the vertical charge transfer channel 20a is illustrated on the upstream side of the CCD line memory section 40.
[0284]
The reference symbols and symbols used in FIG. 23A indicate the same functional elements as the components indicated by the reference symbols or symbols used in FIG. 4 or FIG. Therefore, the description of the components indicated by these reference symbols or symbols is omitted.
[0285]
In the CCD image sensor 10c, horizontal addition of charges can be performed by appropriately selecting the waveforms of the horizontal drive signals φH1 to φH4 and the control signal φLM.
[0286]
FIG. 23B shows the charge distribution in a period from time T1 when the charge is transferred from the CCD line memory section 40 (transfer control stage 40a) to the horizontal charge transfer element 45 to time T5 when the charge is added. Shows the state transition.
[0287]
At time T1, the charge g2 or r is transferred from each vertical charge transfer channel 20a included in the second group Gp2 to the horizontal charge transfer element 45. These charges are distributed in the horizontal charge transfer stage 45a to which the horizontal drive signal φH3 or φH4 is supplied.
[0288]
Next, at time T2, each charge g2 in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage 45a. At time T3, the charges g2 and r in the horizontal charge transfer element 45 are transferred downstream by one horizontal charge transfer stage 45a. Furthermore, at time T4, each charge r in the horizontal charge transfer element 45 is transferred downstream by one horizontal charge transfer stage 45a.
[0289]
Charges g2 are distributed in each of the horizontal charge transfer stages 45a to which the horizontal drive signal φH1 is supplied. The charge r is distributed in each of the horizontal charge transfer stages 45a to which the horizontal drive signal φH2 is supplied.
[0290]
At time T5, charges are transferred from each of the vertical charge transfer channels 20a included in the first group Gp1 to the horizontal charge transfer element 45. The charge g1 is transferred to each of the horizontal charge transfer stages 45a to which the horizontal drive signal φH1 is supplied, and the charge r is transferred to each of the horizontal charge transfer stages 45a to which the horizontal drive signal φH2 is supplied.
[0291]
In each of the horizontal charge transfer stages 45a to which the horizontal drive signal φH1 is supplied, two charges g1 and g2 are added. In each horizontal charge transfer stage 45a to which the horizontal drive signal φH2 is supplied, two charges r are added.
[0292]
Thereafter, each of the added charges g1-g2 is transferred to the downstream side by one horizontal charge transfer stage 45a. The added charges g1-g2 and the added charges rr are distributed every other horizontal charge transfer stage 45a.
[0293]
Thereafter, the horizontal drive signals φH1 and φH3 are set as one set, the horizontal drive signals φH2 and φH4 are set as another set, and each of these sets is changed from the low level L to the high level H, and from the high level H. The repetition level is changed to the low level L. At this time, the phases of the horizontal drive signals φH1 and φH3 are reversed from the phases of the horizontal drive signals φH2 and φH4.
[0294]
Each of the charges g1-g2 and rr in the horizontal charge transfer element 45 is transferred toward the output unit 60 in synchronization with each other.
[0295]
The CCD image sensor 10c capable of driving the horizontal charge transfer element 45 in this way has the same effect as the CCD image sensor 10a according to the first embodiment.
[0296]
Although the CCD image pickup system, the CCD image sensor, and the driving method thereof according to the embodiments have been described above, the present invention is not limited to the above-described embodiments. Various changes, improvements, combinations, and the like are possible.
[0297]
For example, in each of the CCD image sensors according to the embodiment, the first to second horizontal transfer electrodes are provided for each horizontal charge transfer stage by the number before the horizontal transfer electrodes are connected to the voltage supply line. Arranged. However, without changing the structure of the horizontal charge transfer channel, the number of horizontal transfer electrodes before the connection of each horizontal transfer electrode to the voltage supply line can be one per horizontal charge transfer stage. . In this case, the regions covered by the first and second horizontal transfer electrodes are covered with one horizontal transfer electrode. The same applies to the auxiliary horizontal charge transfer stage.
[0298]
In addition, the horizontal charge transfer element has n n-type channels.⁺A charge of the type in which a type impurity doped region and an n type impurity doped region are repeatedly formed in a predetermined pattern, and a predetermined number of transfer electrodes are formed on the n type channel via an electrically insulating film having a substantially constant thickness. It can also be constituted by a transfer element.
[0299]
At this time, the number of each horizontal transfer electrode before the connection to the voltage supply line is the number of individual n⁺One horizontal transfer electrode is disposed above the n-type impurity doped region via an electrical insulating film, and one horizontal transfer electrode is disposed above each n-type impurity doped region via the electrical insulating film. Is done. Or one n⁺Horizontal transfer that covers both of the impurity-added regions constituting this set in a plan view, one for each set of impurity-added regions constituted by the type-doped region and one n-type impurity added region immediately upstream thereof An electrode is arrange | positioned through an electrically insulating film. In addition, the above n⁺An n-type impurity addition region is formed instead of the n-type impurity addition region, an n-type impurity addition region is formed instead of the n-type impurity addition region, and a p formed thereon^-  A region constituted by a type impurity doped region may be formed.
[0300]
A relatively thick region (hereinafter referred to as “thick region”) and a relatively thin region (hereinafter referred to as “thick region”) on one n-type channel where the concentration of the n-type impurity is substantially constant. These regions are referred to as “thin regions”) in a predetermined pattern, an electrical insulating film is formed, and a horizontal direction is formed by a charge transfer element of a type in which a predetermined number of transfer electrodes are formed on the electrical insulating film. A charge transfer element can also be configured.
[0301]
At this time, one horizontal transfer electrode is formed on each of the thick region and the thin region in the number before the horizontal transfer electrode is connected to the voltage supply line. Alternatively, one horizontal region that covers one thick region and one thin region immediately upstream thereof, that covers both the thick region and the thin region constituting the set in plan view. The transfer electrode is disposed via the electrical insulating film.
[0302]
Further, an electrical insulating film having a substantially constant film thickness is formed on one n-type channel having a substantially constant n-type impurity concentration, and a predetermined number of transfer electrodes are formed on the electrical insulating film. A horizontal charge transfer element can also be configured by the type of charge transfer element formed.
[0303]
At this time, by applying a relatively high level voltage to each horizontal transfer electrode, a potential well region can be formed in a region of the n-type channel located under the horizontal transfer electrode. By applying a relatively low level voltage to each horizontal transfer electrode, a potential barrier region can be formed in a region of the n-type channel located under the horizontal transfer electrode.
[0304]
Whichever type of charge transfer element is used as the horizontal charge transfer element, one horizontal charge transfer stage is formed corresponding to one vertical charge transfer element. Each horizontal charge transfer stage has only one potential barrier region and only one potential well region. The horizontal charge transfer stages corresponding to the vertical charge transfer elements are arranged in a row while being adjacent to each other.
[0305]
Each of the horizontal transfer electrodes in the horizontal charge transfer element can be divided into a plurality of groups when the number at the stage after the horizontal transfer electrodes are connected to the voltage supply line is taken as a reference. One group is constituted by m horizontal transfer electrodes (m represents an integer of 3 or more) which are continuous in the photoelectric conversion element row direction, and each of the m horizontal transfer electrodes constituting one group is: They are connected to different voltage supply lines. Each of the horizontal transfer electrodes having a period of m is connected to the same voltage supply line. The value of m can be appropriately selected according to the driving method of the horizontal charge transfer element, such as 3, 4, 6, 7, 8, etc.
[0306]
The driving method of the horizontal charge transfer element is not limited to 6-8 phase driving. It is possible to drive with a desired number of phases equal to or more than three phases according to the intended aspect of horizontal addition.
[0307]
The horizontal addition is not limited to adding two charges, but may be adding three charges or adding four or more desired numbers of charges. In the stage of transferring charges from the horizontal charge transfer element to the output unit, a plurality of types of charges having different numbers of added charges may be distributed in the horizontal charge transfer element.
[0308]
When three charges are horizontally added, each of the vertical charge transfer channels is divided into three groups, and charges are transferred from the CCD line memory unit to the horizontal charge transfer element at different timings for each group. When the four charges are horizontally added, each of the vertical charge transfer channels is divided into four groups, and charges are transferred from the CCD line memory unit to the horizontal charge transfer element at different timings for each group.
[0309]
If the subgroups belonging to the same group are adjacent to each other, the number of auxiliary horizontal charge transfer stages required for transferring charges increases. In addition, charge transfer and horizontal addition in the horizontal charge transfer element become difficult.
[0310]
When color imaging is performed, each of the subgroups constituting one group transfers three types of charges necessary for obtaining full color information, for example, three types of charges g, r, and b. The vertical charge transfer channel is about this number. In the case of black-and-white imaging, it is possible to form one subgroup with one vertical charge transfer channel.
[0311]
In order to suppress a decrease in the resolution of the image displayed on the monitor due to the horizontal addition, it is preferable to horizontally add the same type of charges that are as close as possible in the photoelectric conversion element row direction.
[0312]
Whether or not the auxiliary horizontal charge transfer stage is provided in the horizontal charge transfer element can be appropriately selected.
[0313]
The configuration of the CCD line memory section can also be changed as appropriate, similarly to the horizontal charge transfer element. Any configuration that can form a transfer control stage having one potential barrier region and one potential well region is basically acceptable.
[0314]
The vertical charge transfer element can also be configured without including the auxiliary transfer electrode. The driving method of the vertical charge transfer element is not limited to the driving method based on half-thinning scanning or interlace scanning. Depending on the element structure, imaging mode, vertical addition mode, etc., 1/8 thinning scanning, 1/16 thinning scanning, progressive scanning, etc. can be selected as appropriate. The vertical addition of charges is not necessarily an essential requirement.
[0315]
In a CCD image sensor for color imaging, it is preferable to provide a light shielding film. In a single-plate CCD image sensor for color imaging, a color filter array is provided. Although the microlens array can be omitted, it is preferable to provide the microlens array.
[0316]
In the CCD image sensor for monochrome imaging, the light shielding film and the microlens array can be omitted. Providing a color filter array is not an essential requirement, but a monochromatic color filter array may be provided as necessary.
[0317]
The color filter array provided in the single-plate CCD image sensor for color imaging is not limited to the one having the arrangement pattern shown in FIG. 3 or FIG. The color filter array is not limited to the primary color filter array, and may be a complementary color filter array.
[0318]
As an arrangement pattern of color filters in the primary color filter array, there are known arrangement patterns called Bayer type, interline type, G stripe RB checkered type, G stripe RB complete checkered type, stripe type, diagonal stripe type, etc. Yes. If these arrangement patterns are rotated about 45 ° on a plane, a primary color filter array that can be applied to a CCD image sensor in which a large number of photoelectric conversion elements are arranged in a shifted pixel can be obtained.
[0319]
As the color filter array pattern in the complementary color filter array, there are known array patterns called field color difference sequential type, frame color difference sequential type, MOS type, improved MOS type, frame interleave type, field interleave type, stripe type, etc. ing. If these arrangement patterns are rotated about 45 ° on a plane, a complementary color filter array that can be applied to a CCD image sensor in which a large number of photoelectric conversion elements are arranged in a shifted pixel can be obtained.
[0320]
Regardless of whether the primary color type or the complementary color type color filter array is provided, the color filter array pattern preferably satisfies the following requirements. That is, the number of types of charges necessary for obtaining full-color information, for example, three types of charges, such as charge g, charge r, and charge b, are applied at the same timing and in a certain repeating pattern in the photoelectric conversion element row direction. Can be transferred to the CCD line memory unit.
[0321]
The CCD image sensor is not limited to the interline transfer type, but may be a full frame type, a frame transfer type, a frame interline transfer type, an all pixel readout type, or the like.
[0322]
It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like are possible.
[0323]
【The invention's effect】
As described above, according to the present invention, there is provided a CCD image sensor capable of easily adding desired charges in both the vertical charge transfer element and the horizontal charge transfer element. In the CCD imaging system using this CCD image sensor, it is possible to obtain image data in which both the number of vertical pixels and the number of horizontal pixels are thinned out, so that it is easy to obtain a good reproduced image.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an outline of a CCD imaging system according to an embodiment.
FIG. 2 is a cross-sectional view schematically showing a photoelectric conversion element and its periphery in the CCD image sensor according to the first embodiment.
FIG. 3 is a plan view showing a part of a color filter array provided in the CCD image sensor according to the first embodiment.
FIG. 4 is a partial plan view schematically showing the CCD image sensor according to the first embodiment.
FIG. 5 is an enlarged schematic view showing a region from a CCD line memory section to a horizontal charge transfer element of the CCD image sensor according to the first embodiment.
6A is a schematic view of a cross section taken along line BB shown in FIG. 5, and FIG. 6B is a cross section taken along line CC shown in FIG. FIG.
FIG. 7 is a partial plan view showing one specification of grouping of vertical charge transfer channels performed when performing horizontal charge addition in the horizontal charge transfer element.
8 is a timing chart showing an example of waveforms of a control signal φLM and horizontal drive signals φH1 to φH8 when driving a CCD line memory unit and a horizontal charge transfer element of the CCD image sensor according to the first embodiment, respectively. FIG.
FIGS. 9A and 9B are potentials schematically showing the principle when charges are transferred from the CCD line memory section to the horizontal charge transfer element in the CCD image sensor according to the first embodiment. FIG.
FIGS. 10A to 10B are schematic diagrams showing the state of charge distribution at times t1 to t2 shown in FIG.
FIGS. 11A to 11B are schematic views showing the state of charge distribution at times t3 to t4 shown in FIG.
FIGS. 12A to 12B are schematic diagrams showing the state of charge distribution at times t5 to t6 shown in FIG.
FIGS. 13A to 13B are schematic diagrams showing the state of charge distribution at times t7 to t8 shown in FIG.
FIGS. 14A to 14B are schematic views showing the state of charge distribution at times t9 to t10 shown in FIG.
FIGS. 15A to 15B are schematic views showing the state of charge distribution at times t11 to t12 shown in FIG.
16 is a timing chart showing another example of waveforms of the control signal φLM and the horizontal drive signals φH1 to φH8 when driving the CCD line memory unit and the horizontal charge transfer element of the CCD image sensor according to the first embodiment, respectively. FIG. is there.
FIG. 17 is a partial plan view showing another specification of grouping of vertical charge transfer channels performed when horizontal charge addition is performed in the horizontal charge transfer element.
18A to FIG. 15B are schematic views showing the state of charge distribution at times T1 to T2 shown in FIG.
FIGS. 19A to 19B are schematic diagrams showing the state of charge distribution at times T3 and T5 shown in FIG.
20A to 20B are schematic diagrams illustrating the state of charge distribution at times T7 and T10 illustrated in FIG.
FIG. 21 is a partial plan view schematically showing a planar arrangement of a photoelectric conversion element, a vertical charge transfer element, a CCD line memory section, a horizontal charge transfer element and an output section in a CCD image sensor according to a second embodiment.
FIG. 22 is a plan view showing a part of a color filter array provided in a CCD image sensor according to a second embodiment.
FIG. 23A is a schematic diagram of a CCD image sensor according to a third embodiment, and FIG. 23B is a diagram illustrating a horizontal charge transfer element in the CCD image sensor shown in FIG. It is a schematic diagram which shows a time-dependent change of the distribution state of an electric charge.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10, 10a, 10b, 10c ... CCD image sensor, 11 ... Semiconductor substrate, 15 ... Photoelectric conversion element, 16 ... Photoelectric conversion element area | region, 20 ... Vertical charge transfer element, 20a ... Vertical charge transfer channel, 21 ... Read-out gate, 21a ... Read gate channel region 31, 31a ... First vertical transfer electrode 32, 32a ... Second vertical transfer electrode 40 ... CCD line memory unit 40a ... Transfer control stage 41 ... First transfer control electrode 42 ... Second transfer control electrode, 45 ... Horizontal charge transfer element, 45a ... Horizontal charge transfer stage, 46 ... Horizontal charge transfer channel, 47 ... First horizontal transfer electrode, 48 ... Second horizontal transfer electrode, 55, 55a ... Color filter array , 60 ... output unit, 65 ... drive circuit, 70 ... video signal processing circuit, 80 ... display unit, 100 ... CCD imaging system.

Claims (9)

A semiconductor substrate;
N first charge transfer channel regions of a first conductivity type formed on one surface of the semiconductor substrate;
A charge transfer element including a second charge transfer channel of a first conductivity type formed on the semiconductor substrate and electrically connected to each of the first charge transfer channel regions, Each of the charge transfer stages has a configuration capable of forming a plurality of charge transfer stages arranged in a row corresponding to each one, and each of the charge transfer stages includes only one first potential barrier region and only one And at least N pieces formed on the second charge transfer channel via an electrically insulating film so as to correspond to each of the first charge transfer channel regions. Transfer electrodes, and the N transfer electrodes are configured by a plurality of groups, each of which is a continuous m (m represents an integer of 3 or more), and n of the m transfer electrodes. Pieces (n is m or less positive) Represents an integer.) Is connected to electrically independent voltage supply lines, respectively, a charge transfer element each transfer electrode and the m period is connected to the same voltage supply line,
Each of the charge transfer stages formed in the connection region has a configuration in which at least one charge transfer stage can be formed in a connection region between each of the first charge transfer channel regions and the charge transfer element. A line memory having one second potential barrier region and one second potential well region formed on the second charge transfer channel side of the second potential barrier region;
A drive circuit capable of generating a drive signal or a control signal supplied to each of the line memory and the charge transfer element, wherein a charge corresponding to a desired first charge transfer channel region is selectively selected from the line memory. A drive circuit for transferring to the charge transfer element;
Charge transfer device comprising: The drive circuit selectively transfers charge from a part of the line memory to the charge transfer element, and after transferring at least a part of the transferred charge downstream in the charge transfer element, A charge is selectively transferred from another part of the line memory to the charge transfer element with respect to at least a part of the charge transferred in the charge transfer element, and the charge is added in the charge transfer element. 2. The charge transfer device according to claim 1, wherein m / 2 or less charges are distributed in the charge transfer element per m of the first charge transfer channel regions. The drive circuit divides the N first charge transfer channel regions into X groups (X represents an integer of 2 or more), and each of the first charge transfer channel regions belonging to the first group is included in each of the first charge transfer channel regions. The corresponding charge is transferred from the line memory to the charge transfer element, further transferred inside the charge transfer element and output to the outside, and then corresponds to each of the first charge transfer channel regions belonging to another group The charge to be transferred is transferred from the line memory to the charge transfer element, further transferred inside the charge transfer element and output to the outside, and the charge corresponding to each of the first charge transfer channel regions for each of the X groups. 2. The charge transfer device according to claim 1, wherein charge is transferred from the line memory to the charge transfer element, and the charge transfer element is further transferred to the outside. (i) a semiconductor substrate; (ii) N first charge transfer channel regions of the first conductivity type formed on one surface of the semiconductor substrate; and (iii) the first charge formed on the semiconductor substrate. A charge transfer element including a second charge transfer channel of the first conductivity type electrically connected to each of the transfer channel regions, and arranged in a row corresponding to each of the first charge transfer channel regions. A plurality of charge transfer stages, each of which has only one first potential barrier region and only one first potential well region. And at least one transfer electrode formed on the second charge transfer channel via an electrically insulating film so as to correspond to each of the first charge transfer channel regions. There are m consecutive electrodes (m is 3 Are represented by a plurality of groups, and n of the m transfer electrodes (n represents a positive integer of m or less) are electrically independent voltages. A charge transfer element connected to a supply line and having m transfer electrodes each having a period of m connected to the same voltage supply line; and (iv) between each of the first charge transfer channel regions and the charge transfer element. Each of the charge transfer stages formed in the connection region includes a second potential barrier region, a second potential barrier region, and a second potential barrier region. A line memory having one second potential well region formed on the second charge transfer channel side of the barrier region, and (v) a drive signal or a control signal supplied to each of the line memory and the charge transfer element A drive circuit that can be produced, the desired driving circuit for transferring a charge corresponding to the first charge transfer channel regions to selectively the charge transfer device from the line memory, the charge transfer device provided with A driving method comprising:
Selectively transferring charge from a part of the line memory to the charge transfer element;
Transferring at least part of the charge transferred to the charge transfer element downstream in the charge transfer element;
Adding charge from the line memory to at least part of the charge transferred in the charge transfer element,
A method for driving a charge transfer device, wherein, by the addition, m / 2 or less charges per m of the first charge transfer channel regions are distributed in the charge transfer element. (i) a semiconductor substrate; (ii) N first charge transfer channel regions of the first conductivity type formed on one surface of the semiconductor substrate; and (iii) the first charge formed on the semiconductor substrate. A charge transfer element including a second charge transfer channel of the first conductivity type electrically connected to each of the transfer channel regions, and arranged in a row corresponding to each of the first charge transfer channel regions. A plurality of charge transfer stages, each of which has only one first potential barrier region and only one first potential well region. And at least one transfer electrode formed on the second charge transfer channel via an electrically insulating film so as to correspond to each of the first charge transfer channel regions. There are m consecutive electrodes (m is 3 Are represented by a plurality of groups, and n of the m transfer electrodes (n represents a positive integer of m or less) are electrically independent voltages. A charge transfer element connected to a supply line and having m transfer electrodes each having a period of m connected to the same voltage supply line; and (iv) between each of the first charge transfer channel regions and the charge transfer element. Each of the charge transfer stages formed in the connection region includes a second potential barrier region, a second potential barrier region, and a second potential barrier region. A line memory having one second potential well region formed on the second charge transfer channel side of the barrier region, and (v) a drive signal or a control signal supplied to each of the line memory and the charge transfer element A drive circuit that can be produced, the desired driving circuit for transferring a charge corresponding to the first charge transfer channel regions to selectively the charge transfer device from the line memory, the charge transfer device provided with A driving method comprising:
The N first charge transfer channel regions are divided into X groups (X represents an integer of 2 or more), and charges corresponding to each of the first charge transfer channel regions belonging to the first group are Transferring charges from a line memory to the charge transfer element, further transferring the charge transfer element, and outputting to the outside;
And outputting the electric charge corresponding to each of the first charge transfer channel regions belonging to one other group the transferred charges from the line memory to the charge transfer device, and further transfers the electric charge transferring the element to the outside Including
For each of the X groups, a charge corresponding to each of the first charge transfer channel regions is transferred from the line memory to the charge transfer element, and is further transferred inside the charge transfer element to be output to the outside. A method for driving the transfer device. A semiconductor substrate;
A plurality of photoelectric conversion elements formed in a matrix over a plurality of rows and columns on one surface of the semiconductor substrate;
A plurality of vertical charge transfer elements formed on the semiconductor substrate so as to extend along the photoelectric conversion element array, one for each photoelectric conversion element array;
A CCD line memory unit capable of forming at least one charge transfer stage downstream of each of the vertical charge transfer elements, wherein each of the charge transfer stages follows a corresponding vertical charge transfer element. A CCD line memory unit including a first charge transfer channel region;
A first conductivity type horizontal charge transfer channel formed on the semiconductor substrate and electrically connected to each of the first charge transfer channel regions, and an electrical insulating film above the horizontal charge transfer channel A horizontal charge transfer device having at least N horizontal transfer electrodes formed corresponding to each of the first charge transfer channel regions, wherein the N horizontal transfer electrodes are continuous. m (m represents an integer of 3 or more) is composed of a plurality of groups, and n of the m horizontal transfer electrodes (n represents a positive integer of m or less). Each of the horizontal charge transfer elements is connected to an electrically independent voltage supply line, and each of the horizontal transfer electrodes having a period of m is connected to the same voltage supply line. While corresponding to each one A plurality of horizontal charge transfer stages arranged in a row can be formed, each of the horizontal charge transfer stages having only one first potential barrier region and only one first potential well. A horizontal charge transfer element having a region;
A drive circuit capable of generating a drive signal or a control signal supplied to each of the vertical charge transfer elements, the CCD line memory unit, and the horizontal charge transfer element, and a desired first charge transfer channel region And a drive circuit for selectively transferring the charge corresponding to 1 to the horizontal charge transfer element from the CCD line memory unit ,
The CCD line memory unit includes one second potential barrier region, one second potential well region formed on the second charge transfer channel side of the second potential barrier region, and the second potential. A CCD image sensor including a barrier region and a transfer control electrode disposed above the second potential well region . The driving circuit selectively transfers charges from a part of the CCD line memory unit to the horizontal charge transfer element, and transfers at least a part of the transferred charges downstream in the horizontal charge transfer element. Thereafter, at least a part of the charges transferred in the horizontal charge transfer element is selectively transferred from the other part of the CCD line memory unit to the horizontal charge transfer element, and the horizontal charge is transferred. 7. The CCD image sensor according to claim 6, wherein charges are added in the transfer element to distribute m / 2 or less charges per m of the first charge transfer channel regions in the horizontal charge transfer element. The drive circuit divides the N first charge transfer channel regions into X groups (X represents an integer of 2 or more), and each of the first charge transfer channel regions belonging to the first group is included in each of the first charge transfer channel regions. The corresponding charge is transferred from the CCD line memory unit to the horizontal charge transfer element, further transferred inside the horizontal charge transfer element and output to the outside, and then the first charge transfer channel region belonging to another group Are transferred from the CCD line memory unit to the horizontal charge transfer element, further transferred within the horizontal charge transfer element and output to the outside, and the first charge transfer is performed for each of the X groups. Charge corresponding to each of the channel regions is transferred from the CCD line memory unit to the horizontal charge transfer element, and further transferred inside the horizontal charge transfer element to the outside. CCD image sensor according to claim 6, wherein to force. CCD image sensor according to any one of claims 6 to 8 ,
An output unit disposed in or outside the CCD image sensor and capable of converting a charge output from the horizontal charge transfer element into a signal voltage;
A CCD imaging system comprising: a video signal processing circuit capable of generating image data based on a signal voltage generated at the output unit.

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