JP2525796B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a solid-state imaging device using a CCD (charge coupled device).

(Prior Art) An interline transfer CCD image pickup device includes a plurality of photodiodes for accumulating photoelectrically converted signal charges on a semiconductor substrate, a plurality of columns of vertical CCD registers for reading out the signal charges of the photodiodes, and The vertical CCD register is obtained by integrating and forming a horizontal CCD register for reading the transferred signal charges. In such an interline transfer CCD image pickup device, a plurality of horizontal CCD registers arranged in parallel is known.

Fig. 4 shows a conventional CCD with two rows of horizontal CCD registers.
It is an example of composition of a line type interline transfer type CCD image sensor. A vertical CCD register 2 is provided for each column of photodiodes 1 arranged in a matrix as photosensitive pixels. At the output stage of the vertical CCD register 2, a first horizontal CCD register 4 _A is arranged via a transfer gate 3 and a second horizontal CCD register 4 _B is arranged via a transfer gate 5. The first and second horizontal CCD registers 4 _A and 4 _B are, for example, the same buried channel type in which n-type layers are formed in the channels under the same conditions. Transfer electrodes 6 and 7 are partially formed in common in the horizontal CCD registers 4 _A and 4 _B. Vertical CCD register 2
In the signal charges read in, the signal charges in the odd-numbered columns are transferred to the first horizontal CCD register 4 _A and the signal charges in the even-numbered columns are transferred to the second horizontal CCD register 4 _A , for example.
After being distributed to the horizontal CCD registers 4 _B , they are transferred in parallel. At this time, the odd column vertical
In order to transfer the signal charge of the CCD register 2 to the channel of the first horizontal CCD register 4 _{A and not to} the channel of the second horizontal CCD register 4 _B , the vertical CCDs in odd columns
First and second horizontal CCD registers 4 located below register 2
_A, 4 is a transfer gate 5 under between _B are channel stopper 9 is formed. At the position where the channel stopper 9 is located, the transfer gates 6 and 7 are common to the first and second horizontal CCD registers 4 _A and 4 _B. The signal charge of the vertical CCD register 2 in the even-numbered column passes through the channel of the first horizontal CCD register 4 _A to the second horizontal CCD register 4 _A.
It is necessary to be transferred to the channel of the CD register 4 _B, no channel stopper to under the transfer gate 5 in this position. In this portion, one of the two-phase transfer gates 6 and 7, which is mainly for charge storage, is separated by the first horizontal CCD register 4 _A and the second horizontal CCD register 4 _B. Transfer gates are 6 _A and 6 _B. The other transfer gate 7 is also common in this portion. 1st, 2nd horizontal CC
Two-phase clocks φ _H1 and φ _H2 are applied to the transfer electrodes 6 and 7 of the D registers 4 _A and 4 _B. Since the transfer electrode to which this is applied is divided into 6 _A and 6 _B by the first horizontal CCD register 4 _A and the second horizontal CCD register 4 _B , the clock φ _H2 of the second phase is φ _H2A , divided into φ _H2B, φ _2A line on the first horizontal CCD register 4 _a, phi _H2B are respectively disposed below the second horizontal CCD register 4 _B.

With such a configuration, the signal charge of each pixel obtained by the photodiode 1 is transferred to the vertical CCD register 2 and read by the vertical CCD register 2 for each line to the horizontal CCD register. At this time, the first and second horizontal CCD registers 4 _A , 4 _B
The allocation to is performed as follows. Vertical CCD register 2
First, the signal charge for one line is first set to “H” in the transfer gate 3.
By applying the level clock φ _V1 , the first horizontal
It is read out to the channel of the CCD register 4 _A. At this time, the clocks φ _H1 and φ _H2A are set to the “H” level, and the clock φ _HG is given to the transfer gate 5 between the first and second horizontal CCD registers 4 _A and 4 _B.
And the clock φ _{H2B is set} to the “L” level. After this first
Half of the signal charge of the horizontal CCD register 4 _A of the second horizontal CCD
Transferred to the register 4 _B. This is clock φ _H2A "L"
The level and clocks φ _HG and φ _H2B are set to “H” level, and the signal charge under the transfer electrode 6 _A of the first horizontal CCD register 4 _A is transferred to the transfer electrode of the second horizontal CCD register 4 _B. Transferred under 6 _B. Thus, even-row vertical CCD
The signal charge of the register 2 is transferred to the channel of the second horizontal CCD register 4 _B through the channel of the first horizontal CCD register 4 _A. After this, the first and second horizontal CCD
Transfer and read the signal charges of registers 4 _A and 4 _B in parallel,
By adding these signal charges by shifting their phases by 180 °, an electric signal corresponding to pixels for one line can be obtained. After that, the same operation is repeated to obtain a two-dimensional image signal.

In this two-wire interline transfer CCD image pickup device, the driving frequency of the horizontal CCD register is 1/2 as compared with the case where there is only one horizontal CCD register, and therefore, there is an advantage that driving is easy. However, in the conventional structure as shown in FIG. 4, a vertical black line is recognized on the reproduced image. this is,
This is because a signal charge transfer failure occurs between the first and second horizontal CCD registers 4 _A and 4 _B. The cause of this transfer failure, first, the transfer gate 5 under between second horizontal CCD register 4 _A, 4 _B, vertical
Since the channel stopper 9 is provided for every other CCD register 2, the first
This is probably because a narrow channel effect occurs in the transfer section between the first and second horizontal CCD registers.

As described above, the conventional two-wire interline transfer CCD image pickup device has a problem that the image quality of the reproduced image is deteriorated due to the transfer failure between the horizontal CCD registers.

An object of the present invention is to provide a CCD image pickup device that solves such a problem.

[Structure of the Invention] (Means for Solving Problems) A CCD image pickup device according to the present invention is a horizontal C
With respect to the CD register, the channel impurity concentration of the buried channel is set to be higher as the distance from the vertical CCD register increases, and the transfer electrodes are commonly arranged in the plurality of horizontal CCD registers. No special channel stopper is provided under the transfer gate between the horizontal CCD registers, and basically the same as the channel impurity concentration on the vertical CCD register side.
However, it is preferable that, in the portion for performing the transfer between the horizontal CCD registers, a charge suction port having the same impurity concentration as the channel impurity concentration of the horizontal CCD register farther from the vertical CCD register is formed under the transfer gate.

(Operation) With this configuration, since no special channel stopper is provided under the transfer gate between the horizontal CCD registers,
The narrow channel effect does not occur in the transfer channel section between CCD registers. The distribution of the signal charges from the vertical CCD register to the plurality of horizontal CCD registers is surely performed by the clock control of the transfer gate without the channel stopper. Further, since the transfer gate electrodes of a plurality of horizontal CCD registers are common, clock wiring is easy. Also horizontal
By providing the charge suction port under the transfer gate in the portion where the signal charge is transferred between the CCD registers, defective transfer of the signal charge is further reduced, and an excellent reproduced image can be obtained.

(Example) Hereinafter, the Example of this invention is described with reference to drawings.

FIG. 1 shows the present invention of a two-wire interline transfer type CCD.
It is a schematic plan view of the Example applied to the imaging device. Fourth
The parts corresponding to those of the conventional structure in the figure are denoted by the same reference numerals as in FIG. 4, and detailed description thereof will be omitted. In this embodiment, the channel impurity concentration of the buried channel of the first horizontal CCD register 4 _A, and the higher concentration of that of the second horizontal CCD register 4 _B. Specifically, for example, when a p-type substrate is used, n-type impurities are ion-implanted into the channel regions of the first and second horizontal CCD registers 4 _A and 4 _B and the entire region of the transfer gate 5, and the second By ion-implanting n-type impurities so as to overlap the channel region of the horizontal CCD register 4 _B , a concentration difference is given to the n-type buried channel. Thus, first, the difference in the substrate surface potential between the second horizontal CCD register 4 _A, 4 _B are formed. At this time, the second ion implantation is also performed in a portion of the transfer gate 5 located below the vertical CCD register 2 in an odd number column, and the substrate surface potential in the hatched area in FIG. Get higher That is, the region 8 _B below the odd vertical CCD registers of the transfer gate 5 has the same impurity concentration as the channel of the second horizontal CCD register 4 _B , and the region 8 _B from the channel of the first horizontal CCD register 4 _A second it becomes horizontal CCD register 4 charges suction port in order to ensure a charge transfer to the _B, area under the vertical CCD registers in the even column 8
_A has the same impurity concentration as the channel of the first horizontal CCD register 4 _A. These horizontal CCD registers 4 _A , 4 _B transfer electrodes 6,
7 are commonly arranged.

2-wire interline transfer CCD with such a configuration
The operation of the image sensor will be described below. It is the same as the conventional method that the signal charges of the photodiode 1 are read to the vertical CCD register 2, and the two horizontal CCD registers 4 _A and 4 _B share the signal charges one line at a time and read them in parallel.

FIG. 2 is a clock waveform showing a transfer operation of signal charges from the vertical CCD register 2 to the first and second horizontal CCD registers 4 _A and 4 _B performed in the horizontal blanking period, and FIG. ) To (d) show how the signal charges are transferred, corresponding to times ta to td in FIG. At time ta, as shown in FIG. 3 (a), the clock φ of the vertical CCD register
Signal charges Q ₁ , Q ₂ , Q ₃ , ... _Are stored under the storage electrodes of _{V 3} , φ _{V 4} . At this time, vertical CCD register 2 and horizontal CCD register
The clock φ _BG of the transfer gate 3 between 4 _A is at “L” level. At this time, the first phase clock φ _H1 of the horizontal CCD register is at “H” level and the second phase clock φ _H2 is at “L” level. After that, the clock φ _BG for opening the transfer gate 3 under the vertical CCD register 2 becomes “H” level, and the clocks φ _V3 and φ _{V4 of the} vertical CCD register 2 sequentially become “L” level at time t.
In b, the signal charges Q ₁ , Q ₂ , ... Are transferred below the transfer gate 3. At this time, the horizontal CCD registers 4 _A and 4 _B are clocked by the clock φ _H1.
Is at the “H” level and φ _H2 is at the “L” level, the channel potentials of the horizontal CCD registers 4 _A and 4 _B below the vertical CCD registers 2 in the odd columns become high, so that the signal charges Q ₁ and Q ₃ , Are transferred up to the channel of the first horizontal CCD register 4 _A. In this case the horizontal CCD register 4 _A, the transfer gate 5 between 4 _B clocks phi _HG
Is already at the “H” level, the signal charges Q ₁ , Q ₃ , ... Transferred to the channel of the first horizontal CCD register 4 _A pass directly under the transfer gate 5 to the second horizontal CCD register 4 _A. Four
Transferred to channel _B. As described above, the channel surface potential of the second horizontal CCD register 4 _B is set higher than that of the first horizontal CCD register 4 _A , and the second horizontal CCD register 4 _B is set below the transfer gate 5. Since the charge suction port 8 _B set to the same surface potential as that of the channel is formed, the charge transfer from the channel of the first horizontal CCD register 4 _{A to} the channel of the second horizontal CCD register 4 _B is
Good performance with no leftovers and no crosstalk. The signal charge Q ₂ of the vertical CCD register 2 in the even-numbered column stays below the transfer gate 3 because the channel potential of the horizontal CCD register 4 _A therebelow is low. This is shown in FIG. 3 (b). Next, at the time tc when the clocks φ _BG and φ _HG are set to the “L” level, the transfer gates 3 and 5 are closed, and the clock φ _H2 is set to the “H” level, the signal charge Q ₂ is stored in the first horizontal CCD register 4 Transferred to channel _A. At this time, the surface potential under the transfer gate 5 between the horizontal CCD registers 4 _A and 4 _B is the first horizontal C
Since it is lower than the channel surface potential of the CD register 4 _A , the signal charge Q ₂ stays in the channel of the first horizontal CCD register 4 _A ,
Is not transferred to the second horizontal CCD register 4 _B. That is, under the even-numbered vertical CCD registers, the first horizontal CCD
Although the channel region of the register 4 _A and the region 8 _A of the transfer gate 5 have the same built-in substrate surface potential, the clock φ _HG of the transfer gate 5 is at the “L” level and the clock φ _H2 is at the “H” level. 8 _A has a potential barrier that separates the channels. In this way, the signal charges of the vertical CCD register 2 in the even-numbered column and those in the odd-numbered column are respectively the first and the second.
Of horizontal CCD registers 4 _A , 4 _B. And the first and second
Turning of the channel transfer in the horizontal CCD register 4 _A, 4 _B. Clock φ _H1 First, signal charge at time td when it goes to “L” level
Q _1, Q _2, ... is as shown in FIG. 3 (d), is transferred in parallel to the output terminal of the horizontal CCD register 4 _A, 4 _B at high speed by the well-known two-phase driving after this. The signal charges transferred in parallel are added together with their phases shifted by 180 ° as described above.
It becomes an electric signal for the line. This addition is performed in the state of signal charge in the CCD chip, for example, and an electric signal is taken out from one output terminal to the outside. Alternatively, they may be output separately from the CCD chip and added together by an external circuit.

As described above, in this embodiment, the first and second horizontal CCs
The channel impurity concentration is different between D registers.
No special channel stopper is provided under the transfer gate between the first and second horizontal CCD registers, and the first and second horizontal CCDs are
A charge suction port is provided in a portion where transfer between registers is necessary. Therefore, the narrow channel effect does not occur under the transfer gate in the portion requiring the charge transfer to the second horizontal CCD register, and the good inter-channel charge transfer is performed. As a result, a vertical black line does not occur on the reproduced image, and excellent image quality can be obtained. Also, the first and second horizontal CCDs
All the transfer electrodes of the register are common, and clock wiring to this transfer electrode is easy. Although no special channel stopper is provided between the horizontal CCD registers, the portion that requires inter-channel transfer has a charge inlet with the same impurity concentration as the channel impurity concentration of the second horizontal CCD register. It is also possible to reliably prevent so-called crosstalk in which charges leak to an adjacent transfer stage when the charges are transferred from one horizontal CCD register to the second horizontal CCD register. This also contributes to the improvement of the image quality of the reproduced image.

Although the two-wire type image pickup device has been described in the above embodiments, the present invention can be applied to the case where three rows or more horizontal CCD registers are provided. In particular, the three-wire system is useful, for example, by providing a color stripe filter on the photodiode array and distributing the R, G, B color signals to the three horizontal CCD registers and separately reading them in parallel. Even in that case, the first
A channel impurity concentration of the second horizontal CCD register is higher than that of the second horizontal CCD register and a channel impurity concentration of the third horizontal CCD register is higher than that of the second horizontal CCD register. Good. Further, by providing a signal charge suction port at a required position under the transfer gate between the horizontal CCD registers, as in the above-mentioned embodiment, it is possible to surely prevent the signal charge transfer failure.

Besides, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Advantages of the Invention] As described above, according to the present invention, in a CCD image pickup device having a plurality of rows of horizontal CCD registers, the channel impurity concentrations of the horizontal CCD registers are made different, and the transfer electrodes are commonly used. Without providing a special channel stopper under the transfer gate between the horizontal CCD registers, the signal charges can be distributed to each horizontal CCD register with good controllability, whereby an excellent reproduced image can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing the main configuration of a two-wire interline transfer CCD image sensor according to an embodiment of the present invention, and FIG. 2 is a waveform for explaining the operation of charge transfer to the horizontal CCD register. FIGS. 3 (a) to 3 (d) are diagrams showing the state of signal charges at each timing, and FIG. 4 is a plan view showing a conventional image sensor. 1 ... Photodiode, 2 ... Vertical CCD register, 3
...... Transfer gate, 4 _A・ ・ ・ First horizontal CCD register, 4 _B・ ・ ・
… Second horizontal CCD register, 5 …… Transfer gate, 6,7 ……
Transfer electrode, 8 _B ... Charge inlet.

Claims (2)

(57) [Claims] 1. A plurality of vertical CCD registers in which a plurality of photosensitive pixels are arrayed and formed in a matrix on a semiconductor substrate and the signal charges obtained in each photosensitive pixel are read out, and the output of the vertical CCD register array is provided. Multiple rows of horizontal CCDs adjacent to columns
Registers are arranged so that the transferred signal charges of the vertical CCD register array are distributed to and transferred to a plurality of horizontal CCD registers for each column, and these distributed signal charges are read in parallel by a plurality of horizontal CCD registers. In the solid-state imaging device described above, the plurality of horizontal CCD registers are set such that the channel impurity concentration of the buried channel becomes higher as the distance from the vertical CCD register increases, and the transfer electrodes of the plurality of horizontal CCD registers are commonly used. A solid-state imaging device, which is provided. 2. A transfer gate for controlling signal charge transfer between channels is provided between each of the plurality of horizontal CCD registers, and the transfer gate is provided under the transfer gate and passes through a channel of the horizontal CCD register on the side closer to the vertical CCD register. Horizontal C on the far side
The solid-state imaging device according to claim 1, wherein a signal charge inlet having the same impurity concentration as that of the channel of the horizontal CCD register on the far side is formed in a portion where the signal charge is transferred to the channel of the CD register. apparatus.