JPS6141144B2 - - Google Patents

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Publication number
JPS6141144B2
JPS6141144B2 JP56010671A JP1067181A JPS6141144B2 JP S6141144 B2 JPS6141144 B2 JP S6141144B2 JP 56010671 A JP56010671 A JP 56010671A JP 1067181 A JP1067181 A JP 1067181A JP S6141144 B2 JPS6141144 B2 JP S6141144B2
Authority
JP
Japan
Prior art keywords
heat treatment
film
temperature
silicon substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56010671A
Other languages
Japanese (ja)
Other versions
JPS57124468A (en
Inventor
Masayoshi Ozaki
Yoshikazu Chatani
Osamu Kyogoku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP56010671A priority Critical patent/JPS57124468A/en
Publication of JPS57124468A publication Critical patent/JPS57124468A/en
Publication of JPS6141144B2 publication Critical patent/JPS6141144B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14665Imagers using a photoconductor layer

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Description

【発明の詳細な説明】 本発明は、シリコン基板につくり込まれた多数
のビツトアドレス用MOSトランジスタ上に光導
電膜を設け、この光導電膜を前記MOSトランジ
スタのソース電極に接続してなる固体撮像装置の
製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a solid-state device in which a photoconductive film is provided on a large number of bit addressing MOS transistors built into a silicon substrate, and this photoconductive film is connected to the source electrodes of the MOS transistors. The present invention relates to a method of manufacturing an imaging device.

多数のビツトアドレス用MOSトランジスタ、
フオトダイオードおよびシフトレジスタ用素子等
を単一のシリコン基板につくり込んだ固定撮像装
置は、通常、第1図に示すように構成される。こ
こで、1は多数のMOSトランジスタまたは電荷
転送素子からなる水平シフトレジスタ、2は同様
の垂直シフトレジスタ、3a,3b,……は列ア
ドレス用MOSトランジスタ、4a,4b……は
ビツトアドレス用MOSトランジスタ、5a,5
b…はMOSトランジスタ4a,4b……のソー
ス電極部に形成されたフオトダイオード、6は負
荷抵抗、7はバイアス用電源、8a,8b……は
ポリシリコン等からなる行アドレスライン、9
a,9b……はアルミニウムまたはポリシリコン
等からなる列アドレスライン、10はビデオ信号
出力端子を示す。なお、水平、垂直シフトレジス
タ1,2は2相クロツクパルスCpx,Cpyおよび
シフトパルスSpX,Spyにより駆動される。
Numerous bit address MOS transistors,
A fixed imaging device in which a photodiode, a shift register element, and the like are fabricated on a single silicon substrate is usually constructed as shown in FIG. Here, 1 is a horizontal shift register consisting of a large number of MOS transistors or charge transfer elements, 2 is a similar vertical shift register, 3a, 3b, ... are MOS transistors for column addresses, and 4a, 4b, ... are MOSs for bit addresses. Transistor, 5a, 5
b... are photodiodes formed in the source electrodes of MOS transistors 4a, 4b..., 6 is a load resistor, 7 is a bias power supply, 8a, 8b... are row address lines made of polysilicon, etc., 9
a, 9b, . . . are column address lines made of aluminum or polysilicon, and 10 is a video signal output terminal. The horizontal and vertical shift registers 1 and 2 are driven by two-phase clock pulses C px and C py and shift pulses S pX and S py .

一方、光導電膜を備えた固体撮像装置では、フ
オトダイオード5a,5b……に代えて光導電膜
が適用される。この場合、ビツトアドレス用
MOSトランジスタとそのソース領域に接続され
た光導電膜とは第2図に示すような関係に構成さ
れ、11はP(またはN)導電型のシリコン基
板、12は多数のMOSトランジスタを相互に絶
縁分離するためのフイールド酸化膜、13はN
(またはP)導電型のソース領域、14はN(ま
たはP)導電型のドレイン領域、15はゲート酸
化膜、16はポリシリコンからなるゲート電極、
17はCVD法等により形成された第1の層間絶
縁膜、18a,18bはアルミニウム(シリコン
を含有)またはモリブデン等からなるドレイン電
およびソース電極、19は第2の層間絶縁膜、2
0は光導電膜、21はソース電極18bにオーミ
ツク接触し絶縁膜19上まで延びる光導電膜接続
用電極、22は透明電極を示す。
On the other hand, in a solid-state imaging device equipped with a photoconductive film, a photoconductive film is used in place of the photodiodes 5a, 5b, . . . . In this case, for bit address
The MOS transistor and the photoconductive film connected to its source region are configured in the relationship shown in Figure 2, where 11 is a P (or N) conductivity type silicon substrate, and 12 is a silicon substrate that insulates a large number of MOS transistors from each other. Field oxide film for isolation, 13 is N
(or P) conductivity type source region, 14 is an N (or P) conductivity type drain region, 15 is a gate oxide film, 16 is a gate electrode made of polysilicon,
17 is a first interlayer insulating film formed by CVD method or the like; 18a and 18b are drain and source electrodes made of aluminum (containing silicon) or molybdenum; 19 is a second interlayer insulating film;
0 indicates a photoconductive film, 21 indicates a photoconductive film connecting electrode that is in ohmic contact with the source electrode 18b and extends onto the insulating film 19, and 22 indicates a transparent electrode.

このような装置は、通常、下記の工程により製
造される。まず、シリコン基板に酸化シリコン膜
を熱酸化により一様に形成する。次いで、MOS
トランジスタ形成予定領域を窒化けい素膜で覆
い、選択酸化のための熱処理を施して窒化けい素
膜直下以外の酸化シリコン膜の膜厚を大きくす
る。次いで、窒化けい素膜および直下の酸化シリ
コン膜を順次に除去すると、フイールド酸化膜1
2ができあがる。次に、ゲート酸化膜15用の薄
い酸化シリコン膜およびゲート電極16用のポリ
シリコン膜を順次に形成したのち、そのゲート領
域部分以外をエツチングによりとり除く。次い
で、ドレイン領域14およびソース領域13を熱
拡散またはイオン注入により形成するとともに第
1の層間絶縁膜17用の酸化シリコン膜を形成し
てこれに穴をあけ、ドレイン電極18aおよびソ
ース電極18bを電子ビーム蒸着またはスパツタ
リングにより形成する。こののち、電極18a,
18bと基板11との合金化を兼ねて水素雰囲気
中約430℃の温度下で30分〜60分にわたる加熱処
理を施す。次ぎに、第2の層間絶縁膜19用の酸
化シリコン膜を約1μmの厚さにCVD法で形成
し、この膜19に穴をあけてモリブデン―ニオブ
合金等からなる光導電膜接続用電極21を形成す
る。次いで、約430℃の温度下で再び加熱処理し
たのち、光導電膜20を蒸着により形成し、真空
中約500℃の加熱処理を施す。そして、光導電膜
20上に透明電極22を形成する。
Such a device is usually manufactured by the following steps. First, a silicon oxide film is uniformly formed on a silicon substrate by thermal oxidation. Then, M.O.S.
A region where a transistor is to be formed is covered with a silicon nitride film, and a heat treatment for selective oxidation is performed to increase the thickness of the silicon oxide film other than directly under the silicon nitride film. Next, by sequentially removing the silicon nitride film and the silicon oxide film immediately below, the field oxide film 1 is removed.
2 is completed. Next, a thin silicon oxide film for the gate oxide film 15 and a polysilicon film for the gate electrode 16 are sequentially formed, and then the portions other than the gate region are removed by etching. Next, the drain region 14 and the source region 13 are formed by thermal diffusion or ion implantation, and a silicon oxide film for the first interlayer insulating film 17 is formed and holes are formed therein, and the drain electrode 18a and the source electrode 18b are Formed by beam evaporation or sputtering. After this, the electrode 18a,
Heat treatment is performed for 30 to 60 minutes at a temperature of about 430° C. in a hydrogen atmosphere to also alloy the substrate 18b and the substrate 11. Next, a silicon oxide film for the second interlayer insulating film 19 is formed to a thickness of about 1 μm by the CVD method, and a hole is made in this film 19 to form a photoconductive film connecting electrode 21 made of a molybdenum-niobium alloy or the like. form. Next, after heat treatment is performed again at a temperature of approximately 430° C., a photoconductive film 20 is formed by vapor deposition, and heat treatment is performed at approximately 500° C. in vacuum. Then, a transparent electrode 22 is formed on the photoconductive film 20.

このような光導電膜付き固体撮像装置は、光感
度、残像およびブルーミング等において良好な特
性を示すのであるが、光導電膜20の下地として
のMOS集積回路のしきい値電圧が、装置の製造
工程中に変化し易い問題点があつた。
Such a solid-state imaging device with a photoconductive film exhibits good characteristics in terms of photosensitivity, afterimage, blooming, etc. However, the threshold voltage of the MOS integrated circuit as the base of the photoconductive film 20 is determined by the manufacturing process of the device. There were problems that could easily change during the process.

前記しきい値電圧は種々の要因によつて変化す
るが、その一つにシリコン基板11とゲート酸化
膜15との間に生じたダングリンボンドがある。
このダングリングボンドは、シリコン基板11を
高温下で酸化処理したときに生じたもので、これ
が界面準位になることによつてしきい値電圧に変
化をきたす。前記ダングリングボンドは、前述し
た水素雰囲気中での加熱処理を施すことによつて
消失せしめうるが、シリコンと結合した水素は不
安定なものであるから、その後の加熱処理、すな
わち第2の層間絶縁膜19をCVD法(反応温度
は約400℃)により形成する段階、とりわけ結晶
質光導電膜20を真空中約500℃で加熱処理する
段階で水素脱離を生じ、しきい値電圧を変化させ
る。
The threshold voltage changes depending on various factors, one of which is the dangling bond generated between the silicon substrate 11 and the gate oxide film 15.
This dangling bond is generated when the silicon substrate 11 is oxidized at high temperature, and when it becomes an interface state, the threshold voltage changes. The dangling bonds can be eliminated by performing the heat treatment in the hydrogen atmosphere described above, but since hydrogen bonded to silicon is unstable, the subsequent heat treatment, that is, the second interlayer Hydrogen desorption occurs during the step of forming the insulating film 19 by the CVD method (reaction temperature is about 400° C.), especially the step of heat-treating the crystalline photoconductive film 20 at about 500° C. in vacuum, changing the threshold voltage. let

さらにまた、ドレイン電極18aおよびソース
電極18bを、たとえばシリコン含有のアルミニ
ウムより形成するさい、電子ビーム蒸着で生じた
軟X線またはスパツタリングで生じた紫外線によ
り、シリコン基板11に構造欠陥を生じることが
あり、この場合もしきい値電圧に変化をきたす。
そこで、ドレイン電極18aとシリコン基板11
との合金化を兼ねて水素雰囲気中430℃付近での
加熱処理30分〜60分にわたり施している。しか
し、次いで厚さ約1μの第2の層間絶縁膜19を
CVD法(反応温度は約400℃)により形成する過
程で、前記合金化がさらに進行する結果、ドレイ
ン電極18aに若干の移動が起こり、第2の層間
絶縁膜19にクラツクを生じるという事態を招
く。
Furthermore, when forming the drain electrode 18a and the source electrode 18b from silicon-containing aluminum, for example, structural defects may occur in the silicon substrate 11 due to soft X-rays generated during electron beam evaporation or ultraviolet rays generated during sputtering. , this also causes a change in the threshold voltage.
Therefore, the drain electrode 18a and the silicon substrate 11
Heat treatment is performed at around 430°C in a hydrogen atmosphere for 30 to 60 minutes to form an alloy with the metal. However, next, a second interlayer insulating film 19 with a thickness of about 1 μm was formed.
During the formation process using the CVD method (reaction temperature is about 400° C.), as the alloying progresses further, the drain electrode 18a moves slightly, causing a crack in the second interlayer insulating film 19. .

本発明は、シリコン基板11に生じた構造欠陥
を解消させるべく施した前記第1の加熱処理の効
果および前記クラツクの発生が、その後に施す加
熱処理の処理温度に大きく左右されること、すな
わち、水素雰囲気中での第1の加熱処理後に水素
雰囲気中でない高温での加熱処理を施すと、水素
脱離を生じて構造欠陥解消の効果が満足に得られ
ず、しかも層間絶縁膜19にクラツクを生じやす
いという点に着目してなされたものである。
The present invention is characterized in that the effect of the first heat treatment performed to eliminate structural defects generated in the silicon substrate 11 and the occurrence of the cracks are largely influenced by the processing temperature of the subsequent heat treatment, that is, If heat treatment is performed at a high temperature other than in a hydrogen atmosphere after the first heat treatment in a hydrogen atmosphere, hydrogen desorption occurs and the effect of eliminating structural defects cannot be obtained satisfactorily, and furthermore, the interlayer insulating film 19 is cracked. This was done with a focus on the fact that it is more likely to occur.

本発明の固体撮像装置の製造方法によれば、ド
レイン電極18aおよびソース電極18bを形成
した後に施す水素雰囲気中での第1の加熱処理の
処理温度を、従来よりも若干高い450℃〜550℃に
設定するとともに、光導電膜接続用電極21を形
成したのちに施す水素雰囲気中での第2の加熱処
理の処理温度を、前記第1の加熱処理の処理温度
よりも少なくとも5℃低い値に設定する。
According to the method for manufacturing a solid-state imaging device of the present invention, the processing temperature of the first heat treatment in a hydrogen atmosphere, which is performed after forming the drain electrode 18a and the source electrode 18b, is set at 450°C to 550°C, which is slightly higher than the conventional temperature. At the same time, the processing temperature of the second heat treatment in a hydrogen atmosphere performed after forming the photoconductive film connecting electrode 21 is set to a value at least 5° C. lower than the processing temperature of the first heat treatment. Set.

つぎに本発明の実施例を示す。ただしドレイン
電極18aおよびソース電極18bを形成するま
での工程は、前述した従来の工程と変りがないの
で、その説明は省略する。電極18a,18bを
形成したのちのシリコン基板11に、30分以上に
わたり水素雰囲気中450℃〜550℃、好ましくは
470℃〜500℃の温度で第1の加熱処理を施す。次
に、酸化シリコンからなる厚さ0.5μ〜1.0μの第
2の層間絶縁膜19をCVD法(反応温度は約400
℃)により形成し、しかるのち、Mo―Nb合金ま
たはZr等からなる光導電膜接続用電極21を、電
子ビーム蒸着またはスパツタリングにより形成す
る。この段階においてもシリコン基板11の表面
部分に軟X線または紫外線による構造欠陥を生じ
るので、次いで水素雰囲気中での第2の加熱処理
を施して、脱離した水素の補充をしておく。ただ
し、この第2の加熱処理は、前記第1の加熱処理
温度よりも少なくとも5℃低い温度(420℃〜545
℃)下で行う。
Next, examples of the present invention will be shown. However, the steps up to forming the drain electrode 18a and the source electrode 18b are the same as the conventional steps described above, so a description thereof will be omitted. After forming the electrodes 18a and 18b, the silicon substrate 11 is heated at 450°C to 550°C, preferably in a hydrogen atmosphere for 30 minutes or more.
A first heat treatment is performed at a temperature of 470°C to 500°C. Next, a second interlayer insulating film 19 made of silicon oxide with a thickness of 0.5 μm to 1.0 μm is deposited using the CVD method (reaction temperature is approximately 400 μm).
After that, a photoconductive film connecting electrode 21 made of Mo--Nb alloy, Zr, etc. is formed by electron beam evaporation or sputtering. Even at this stage, structural defects occur on the surface portion of the silicon substrate 11 due to soft X-rays or ultraviolet rays, so a second heat treatment is then performed in a hydrogen atmosphere to replenish the desorbed hydrogen. However, this second heat treatment is performed at a temperature that is at least 5 degrees Celsius lower than the first heat treatment temperature (420 degrees Celsius to 545 degrees Celsius).
℃).

第1の加熱処理温度を高くしたため、前記合金
化がこの加熱処理でほぼ完了し、第2の層間絶縁
膜19の形成時に、ドレイン電極18aとシリコ
ン基板11との合金化が進行することはほとんど
なくなり、第2の層間絶縁膜19にクラツクを生
じることが防止される。また、シリコン基板11
の表面部分に生じた構造欠陥は、第2の加熱処理
による水素の補充でほぼ完全に解消する。なお、
第1の加熱処理を500℃に設定したとき、第2の
加熱処理を470℃に設定することができる。どれ
だけ下げるかは、第1の加熱処理時間の長短とも
関係し、第1の加熱処理時間が60分なら20℃〜30
℃低め、30分なら5℃〜20℃低めという目安でも
よい。また、第2の加熱処理時間も約30分〜60分
でもよい。
Since the first heat treatment temperature is set high, the alloying is almost completed by this heat treatment, and the alloying between the drain electrode 18a and the silicon substrate 11 hardly progresses when the second interlayer insulating film 19 is formed. This prevents cracks from occurring in the second interlayer insulating film 19. In addition, the silicon substrate 11
Structural defects occurring on the surface of the substrate are almost completely eliminated by replenishing hydrogen through the second heat treatment. In addition,
When the first heat treatment is set at 500°C, the second heat treatment can be set at 470°C. How much to lower the temperature is also related to the length of the first heat treatment time; if the first heat treatment time is 60 minutes,
A good guideline is to lower the temperature by 5°C to 20°C for 30 minutes. Further, the second heat treatment time may also be approximately 30 minutes to 60 minutes.

第2の加熱処理を施したのち、光導電膜20お
よび透明電極22を形成する。光導電膜20がた
とえばZn―Seを第1層とし、(ZnTe)1-y
(In2Te3yを第2層、CdTeを第3層、ZnSeを第
4層とする4層構造の場合、シリコン基板11を
約250℃の温度に保つて第1層を約0.2μの厚さに
蒸着し、次に、シリコン基板11を約180℃に保
つて第2層を約1μの厚さに、第3層を約0.5μ
の厚さにそれぞれ蒸着する。そしてシリコン基板
11を約250℃の温度に保つて第4層を約0.2μの
厚さに蒸着する。こののち、真空中約500℃での
加熱処理を数分間にわたり行うが、この加熱によ
る水素脱離でしきい値電圧および界面準位密度に
変化を生じることはほとんどなかつた。とくに、
最後の真空中熱処理の温度を470℃以下に選ぶこ
とによつては、全く変動が認められず、第2の層
間絶縁膜にクラツクを生じることもなく、良好な
固体撮像装置を得ることができた。
After performing the second heat treatment, a photoconductive film 20 and a transparent electrode 22 are formed. The photoconductive film 20 has, for example, Zn--Se as the first layer, (ZnTe) 1-y
(In 2 Te 3 ) In the case of a four-layer structure in which y is the second layer, CdTe is the third layer, and ZnSe is the fourth layer, the silicon substrate 11 is kept at a temperature of about 250°C and the first layer has a thickness of about 0.2μ. Next, the silicon substrate 11 is kept at about 180°C, and the second layer is about 1μ thick, and the third layer is about 0.5μ thick.
Each layer is deposited to a thickness of . Then, the fourth layer is deposited to a thickness of about 0.2 μm while keeping the silicon substrate 11 at a temperature of about 250° C. After this, heat treatment was performed at about 500° C. in vacuum for several minutes, but the hydrogen desorption caused by this heating hardly caused any changes in the threshold voltage or interface state density. especially,
By selecting the temperature of the final vacuum heat treatment to be 470° C. or lower, no fluctuation is observed and no cracks occur in the second interlayer insulating film, making it possible to obtain a good solid-state imaging device. Ta.

なお、以上は結晶質光導電膜使用の実施例につ
きのべたが、非晶質光導電膜を備えた固体撮像装
置にも適用でき、とくに装置の封止またはパツキ
ング工程において高温加熱処理を必要とするもの
に適用してすぐれた効果を奏する。
Although the above has been described as an example using a crystalline photoconductive film, it can also be applied to a solid-state imaging device equipped with an amorphous photoconductive film, especially when high-temperature heat treatment is required in the device sealing or packing process. It has excellent effects when applied to things that require

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は固体撮像装置の一般的な回路構成を示
す回路図、第2図は光導電膜付き固体撮像装置の
要部拡大断面図である。 11……シリコン基板、13……ソース領域、
14……ドレイン領域、17……第1の層間絶縁
膜、18a……ドレイン電極、18b……ソース
電極、19……第2の層間絶縁膜、20……光導
電膜、21……光導電膜接続用電極。
FIG. 1 is a circuit diagram showing a general circuit configuration of a solid-state imaging device, and FIG. 2 is an enlarged sectional view of a main part of the solid-state imaging device with a photoconductive film. 11...Silicon substrate, 13...Source region,
14... Drain region, 17... First interlayer insulating film, 18a... Drain electrode, 18b... Source electrode, 19... Second interlayer insulating film, 20... Photoconductive film, 21... Photoconductive Electrode for membrane connection.

Claims (1)

【特許請求の範囲】[Claims] 1 シリコン基板にMOSトランジスタのドレイ
ン領域およびソース領域を形成したのち、第1の
層間絶縁膜を形成し、次いで、前記ドレイン領域
にオーミツク接触するドレイン電極および前記ソ
ース領域にオーミツク接触するソース電極を前記
絶縁膜上に形成して、水素雰囲気中450℃〜550℃
の温度で第1の加熱処理を施し、次いで、前記ド
レイン電極を第2の層間絶縁膜で覆つたのち、前
記ソース電極にオーミツク接触しかつ前記第2の
層間絶縁膜上まで延びる光導電膜接続用電極を形
成し、しかるのち水素雰囲気中で前記第1の加熱
処理よりも少なくとも5℃低い温度で第2の加熱
処理を施し、次いで、前記光導電膜接続用電極上
に光導電膜を形成して加熱処理することを特徴と
する固体撮像装置の製造方法。
1 After forming a drain region and a source region of a MOS transistor on a silicon substrate, a first interlayer insulating film is formed, and then a drain electrode in ohmic contact with the drain region and a source electrode in ohmic contact with the source region are formed in the silicon substrate. Formed on an insulating film and heated at 450℃ to 550℃ in a hydrogen atmosphere
After performing a first heat treatment at a temperature of After that, a second heat treatment is performed in a hydrogen atmosphere at a temperature at least 5° C. lower than the first heat treatment, and then a photoconductive film is formed on the photoconductive film connecting electrode. 1. A method for manufacturing a solid-state imaging device, comprising heating the solid-state imaging device.
JP56010671A 1981-01-26 1981-01-26 Manufacture of solid image pickup device Granted JPS57124468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56010671A JPS57124468A (en) 1981-01-26 1981-01-26 Manufacture of solid image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56010671A JPS57124468A (en) 1981-01-26 1981-01-26 Manufacture of solid image pickup device

Publications (2)

Publication Number Publication Date
JPS57124468A JPS57124468A (en) 1982-08-03
JPS6141144B2 true JPS6141144B2 (en) 1986-09-12

Family

ID=11756707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56010671A Granted JPS57124468A (en) 1981-01-26 1981-01-26 Manufacture of solid image pickup device

Country Status (1)

Country Link
JP (1) JPS57124468A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6598436B2 (en) * 2014-08-08 2019-10-30 キヤノン株式会社 Photoelectric conversion device, imaging system, and method of manufacturing photoelectric conversion device

Also Published As

Publication number Publication date
JPS57124468A (en) 1982-08-03

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